參數(shù)資料
型號(hào)： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 20/46頁(yè)
文件大?。?/td> 212K
代理商： MB86976PF-G
MB86976
Fujitsu Microelectronics, Inc.
27
Advanced 11/5/98
LAN_TxControl (LAN Transmit Control, Register 08)
This register affects the way in which Ethernet traffic is being transmitted on the LAN interface.To receive an interrupt after each packet,
set the enable completion and all the MAC error enable bits and clear bit 12, MacTxInterrupt, of the INTerruptMASK, reg 42h.
Interrupts may also be enabled only for specific conditions.
MAC_TxStatus (Register 0C)
The transmission status flags are set whenever the corresponding event occurs. In addition, an interrupt is generated if the corresponding
enable bit in the transmit control register is set and bit 12, MacTxInterrupt, of the INTerruptMASK, reg 42h, is cleared.
The low order five bits can be read and masked as a single collision count, i.e when ExColl is 1, TxColl is 0. If TxColl is non-zero, then
ExColl is 0.
Bit
Symbol
Type
Description
0
Tx_EN
RW0
Transmit Enable: If zero, stop transmission immediately.
1
Tx_Halt
RW0
Transmit Halt Request: Halt transmission after completing any current packet.
2
No_Pad
RW0
Suppress Padding: Do not generate pad bytes for packets with less than 64 bytes.
3
No_CRC
RW0
Suppress CRC: Do not add the CRC at the end of a packet.
4
0
N
Reserved: Write 0
5
No_Def
RW0
No Defer: Disable the defer counter and excessive deferral checking.
7:6
0
N
Reserved: Unassigned.
8
En_Under
RW0
Enable Underrun: Interrupt if the MAC transmit FIFO becomes empty during transmission.
9
En_Ex_Defer
RW0
Enable Excessive Deferral: Interrupt if the MAC defers for MAX_DEFERRAL time = 3.2768 ms
for 10 Mbits/s
10
En_No_Carr
RW0
Enable No Carrier: Interrupt if carrier sense is not detected during the transmission of a packet.
11
En_Ex_Coll
RW0
Enable Excessive Collision: Interrupt if 16 collisions occur in the same packet.
12
En_Late_Coll
RW0
Enable Late Collision: Interrupt if a collision occurs after 512 bit times (64 byte times).
13
En_Tx_Par
RW0
Enable Transmit Parity: Interrupt if the MAC transmit FIFO has an internal parity error.
14
En_Compl
RW0
Enable Completion: Interrupt when the MAC transmits or discards one packet.
15
0
N
Reserved: Unassigned.
Bit
Symbol
Type
Description
3:0
TxColl
R0
Count of the collisions in transmitting a single packet. If 16 collisions occur, TxColl will be zero, and
ExColl is set.
4
ExColl
R0
Set if 16 collisions occur in the same packet. Transmission skipped.
6:5
N
Reserved
7
IntTx
R0
Set if transmission of packet caused any interrupt condition (includes En_Compl).
8
Underrun
R0
MAC transmit FIFO becomes empty during transmission.
9
Ex_Defer
R0
MAC defers for MAX_DEFERRAL: = 3.27680 ms for 10 Mbits/s
10
NO_CarrS
R0
Carrier sense is not detected during the transmission of a packet (from SFD to CRC).
11
Tx10Stat
R0
= 1 if packet was transmitted via the 10-Mb/s interface, = 0 invalid internal mode.
12
LateColl
R0
A collision occurs after 512 bit times (64 byte times).
13
TxPar
R0
MAC transmit FIFO has detected a parity error (internal error, may clear Tx_En).
14
Tx_Compl
R0
Completion: MAC transmits or discards one packet.
15
TxHalted
R0
Transmission was halted by clearing Tx_En or setting TxHalt.
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