參數(shù)資料
型號(hào)： MB86976PF-G
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 3/46頁(yè)
文件大小： 212K
代理商： MB86976PF-G
MB86976
Fujitsu Microelectronics, Inc.
11
Advanced 11/5/98
LAN Interface
The LAN Interface controls transmission and reception of frame
data on the LAN link. The MB86976 incorporates a fully
functional 10 Mbps Ethernet Media Access Controller (MAC)
core. Outputs are provided for receive, transmit, collision, and link
test LEDs.
The MAC interfaces with an external transceiver (such as the
Fujitsu MB86961A Universal Interface for 10BASE-T) using a
10 Mbps serial interface. The MAC presents and expects the raw
Ethernet frame as a bitstream to and from the transceiver.
Manchester encoding/decoding and all additional signalling is
performed by the transceiver.
MAC Register Map
The MAC contains registers to control its operation, report on
status, and return statistics on device operation. They are accessed
as a subset of the MB86976’s overall register set, and from the
processor’s perspective, are no different from other registers. The
address map and a basic description of the register set are listed
under the section headed“Functional Control and Status
Registers” on page 23.
Lan Data Transfer
All transfers of LAN frame data occur between the Memory
Controller and the internal MAC. Received frames are transferred
to a temporary buffer in the Memory Controller before being
transferred to the frame buffer in the external DRAM. The filter
engine accesses received frame data from this temporary buffer
within the Memory Controller. Frames originating in the
processor or the WAN must first be transferred to this frame buffer,
where they are queued for transmission.
Operation
The Ethernet MAC operates under control of the external processor.
Transmission and reception must be configured through writes to
the LAN_TxControl (LAN Transmit Control), LAN_RxControl
(LAN Receive Control), and MAC_CTL (MAC Control) registers.
Once configured, normal MAC operation requires a minimum of
intervention by the processor.
Information regarding transmission of data through the MAC core
is given for informational value only. The operation here is
transparent to the user.
Transmission
Once the MAC transmission function is enabled through a write to
the transmit enable bit of the Transmit Control register, the MAC
is capable of transmitting frames. The Memory Controller can
begin writing data to the Transmit FIFO at any time. The MAC
will wait for 64 bytes of data to be written before acquiring the
network link, so that back-off with retransmission is possible
without extra intervention.
As long as there is space, the Memory Controller can feed
additional frame data to the MAC Transmit FIFO. To maximize
usage of Fast Page Mode memory access, the Memory Controller
will transfer frame data in 4-word blocks whenever that amount of
data is available. When passing the final byte of frame data, the
Memory Controller indicates an end of frame. The MAC then
completes the transmission, and sets the transmit status registers.
The MAC also implements the interframe gap without processor
intervention.
Reception
The reception process begins once the CPU has configured the
MB86976 MAC by writing to the Rx_EN (receive enable) bit of
the LAN_RxControl register. Once in operation, the MAC
monitors the data passed to it by the physical layer and checks for
valid frames. If it identifies a frame preamble, it will begin
reception. The MAC strips the preamble and Start Frame
Delimiter (SFD) from the frame and begins calculation of the
CRC. Once the MAC receives 8 Bytes in the 16-Byte receive FIFO it
will signal that the Memory Controller must accept data from it at
its earliest convenience. The MAC then exchanges data with the
Memory Controller. This process is repeated until the frame is
entirely received, when the MAC will set the receive status registers.
Interrupts
There are a number of transmit and receive interrupt options. They
are configured by setting the appropriate bits of the MAC Receive
and Transmit Control registers. They are masked by clearing these
bits. Even when these interrupts are not set, the Receive and
Control Status registers record for each frame whether a given
interrupt would have been asserted, so that the processor may poll
the status registers to determine interrupt status without suffering
the penalty of a hardware interrupt.
相關(guān)PDF資料
PDF描述
MB87033BPF SCSI BUS CONTROLLER, PQFP80
MB8867P 21.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP24
MB88R157A OTHER CLOCK GENERATOR, PDSO8
MB89498PMC 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP100
MB89F051PMC 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86977 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
MB86977PFV-G-BND 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
MB86A21PMC-G-BNDE1 制造商:FUJITSU 功能描述:
MB86A21PMC-G-JNE1 制造商:FUJITSU 功能描述:
MB86A22PMC-ES-BNDE1 制造商:FUJITSU 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*