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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大小： | 212K |
| 代理商： | MB86976PF-G |
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MB86976
Fujitsu Microelectronics, Inc.
23
Advanced 11/5/98
Reset
The MB86976 has a single reset input, RESET, and synchronizes
this input and distributes it throughout the chip as a synchronous
reset signal. The MB86976 makes the assumption that the system
clock will be available during system reset. The mimimum period
for RESET assertion is 2 SYSCLK periods.
Following reset, all on-board state machines are set to begin
operation only after configuration by the processor. The Ethernet
MAC will undergo both hardware and software reset operations
when driven by the RESET pin.
The MB86976 will not begin operation until signalled by
processor writes to the appropriate transmit/receive control
registers.
JTAG Support
The MB86976 supports both scan testing and IEEE 1149.1
Boundary Scan. The Boundary Scan Controller is accessible
through the
standard JTAG Interface (via TCK, TMS, TDI, TDO, and JTRST
signals). Boundary Scan cells are present on all chip I/O, including
monitor-only cells on the system clock pins.
The MB86976 Scan testing is independent of the JTAG interface
and has a total of seven scan chains. They are accessible through an
independent pin (TMS) which toggles between scan mode and
system mode. The scan data in and out are multiplexed with
existing pins and selected by SCANTESTMODE for this purpose.
For details contact the factory.
Functional Control and Status Registers
The control and status registers on the MB86976 are accessed
through direct register addresses x000H through x100H. Some of
the registers listed in the Internal Register Address Map are not
required/supported for normal operation. They are provided for
test purposes at the factory and will not be discussed.
Type Description (TYPE)
The following legend of descriptions applies to the type column of
the register bit description tables:
R:
Readable bit.
W:
Writable bit.
C:
Clears associated status bit and/or interrupt
when 1 is written: no effect when 0 is written.
N:
Not used: reserved; write only 0 when written.
0/1: Initial state after hardware reset.
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相關代理商/技術參數(shù) |
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