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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 37/46頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
42
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
Software DMA and FrameBuffer Procedures
Procedure for completing a DMA write to the MB86976:
1.
Write the physical memory address into register
DMA_StartAddress, register 50. This will require 3 byte-wide
writes to the 18-bit register, with the top 6 bits of the high-order
byte ignored.
2.
Write the number of 16-bit words to be written into register
DMA_Length, register 54. The maximum number is eight.
3.
Write the words to be written, starting with the low-order byte of
the first word, followed by the high-order byte of the first word,
and then repeat as necessary. The register (FIFO) for these writes
is DMA_FIFO, register 5E. An uneven number of bytes is OK,
but the data written into the MSB of the incomplete word will be
unknown.
4.
Write a 1 to the LSb of register DMA_Write_GO, register 5A.
5.
Wait for interrupt DMA_Done, register 40, bit 6.
6.
Repeat as necessary.
Procedure for completing a DMA read to the RCB:
1.
Write the physical memory address into register
DMA_StartAddress, register 50. This will require 3 byte-wide
writes to the 18-bit register, with the top 6 bits of the high-order
byte ignored.
2.
Write the number of 16-bit words to be written into register
DMA_Length, register 54. The maximum number is eight.
3.
Write a 1 to the LSb of register DMA_Read_GO, register 56.
4.
Wait for interrupt DMA_Done, register 40, bit 6.
5.
Read the correct number of words from register (FIFO)
DMA_FIFO, register 5E. In byte-wide data mode, the entire last
word must be read, even if only the low-order byte is of interest.
6.
Repeat as necessary.
Procedure for receiving a frame from the MB86976:
1.
Wait for interrupt Proc_Bnd_Pkt, register 40, bit 8.
2.
Poll the LSb of register FrB_Read_GO, register 4E, until it is set.
3.
Read 4 16-bit words from register (FIFO) FrameBuffer, register
48. In byte-wide data mode, the first byte read is the LSB of the
first word.
4.
Once again, poll the LSb of register FrB_Read_GO, register 4E,
until it is set.
5.
Repeat steps 3 and 4. The first read word will be the header,
which is used to determine the correct number of words to read.
The frame should be read in 4-word blocks until the end, and then
the last partial block should be read. Reads using byte-wide data
should complete a whole-word, even if there are an odd number of
bytes in the frame.
Procedure for sending a frame to the MB86976:
1.
Write the header word and first 3 data (frame) words to register
(FIFO) FrameBuffer, register 48.
2.
Write a 1 to the LSb of register FrB_Write_GO, register 4C.
3.
Wait for interrupt Proc_Wr_Compl, register 40, bit 10.
4.
Repeat writes in groups of 4 words.
5.
At the end of the frame, write the partial block of 4 words to the
FrameBuffer, register 48.
6.
Instead of writing to FrB_Write_GO, register 4C, write a 1 to the
LSb of register End_of_Frame, register 4A.
7.
Wait for interrupt Proc_Wr_Compl, register 40, bit 10, or
Proc_Buf_Full, register 40, bit 9. If Proc_Buf_Full is asserted,
the buffer was full and the frame was not stored for transmission.
Repeat the tranmission in its entirety. If Proc_Wr_Compl is
asserted, the frame was stored and will be transmitted. Note that
Proc_Buf_Full is evaluated at the same time as Proc_Wr_Compl,
so there is no danger that a successful transmission could be incor-
rectly signalled.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
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