參數(shù)資料
型號(hào)： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 5/46頁(yè)
文件大?。?/td> 212K
代理商： MB86976PF-G
MB86976
Fujitsu Microelectronics, Inc.
13
Advanced 11/5/98
already contain PPP protocol fields, while LAN packets will not.
The header fields that must be transmitted will have their values
read in from the appropriate MB86976 registers: HDLC_address,
HDLC_control, PPP_Protocol, LEX_FIZ0 and LEX_MacType.
The values in these registers are transmitted least significant bit
first.
WAN frames sourced from the CPU (instead of the LAN port) will
not have the PPP specific fields automatically added by the
hardware, and so firmware must explicitly prepend the appropriate
data to the frame it has constructed. The Memory Controller
informs the WAN Interface of the originator of the packet so that it
may choose the appropriate encapsulation.
If the WTXE pin is asserted, the MB86976 places bits onto WTXD
synchronous with every falling edge of WTXC. If a frame is ready
and the WAN_Tx_ENable bit in WAN_TxControl is hi, the WAN
Interface then begins transmitting the data loaded in the transmit
FIFO, otherwise HDLC flags (01111110) are transmitted. A zero
bit will be inserted after each occurrence of five consecutive one
bits, as per the HDLC protocol for synchronous transmission.
When WTXE is deasserted, the MB86976 halts transmission.
In parallel, the FCS checksum generator computes the FCS for the
current frame prior to zero insertion. After the Memory Controller
reaches the end of the frame and the final data words from the
FIFO have been transmitted, the generated FCS followed by an
HDLC flag is transmitted to complete the WAN packet.
While the FCS is being transmitted, the WAN Interface indicates
to the Memory Controller that another transmission may be
initiated, since free space will exist in the transmit FIFO. If a
second frame is currently queued in the frame buffer, it can be
loaded into the FIFO, and back-to-back transmission can be
achieved. The WAN Interface transmits the next frame after the
previous frame has completed and at least one flag sequence has
been transmitted. If the transmit FIFO is not full at the completion
of the flag sequence, the flag sequence will be repeated until a full
FIFO is detected.
Reception
The WAN Interface receive module will operate with a receive clock
up to a maximum frequency of 8.2 MHz. On each positive
transition of WRXC that is accompanied by an active WRXE, the
receive logic samples WRXD and stores the sampled bit in the open
position of an 8-bit serial-to-parallel register. Logic attached to
this register continually senses for an 8-bit sequence that matches
the HDLC flag (01111110). Once this flag is identified,
subsequent bits are considered to be the input data stream unless
and until another flag sequence is encountered. Zero stripping is
also completed in this module following the receipt of five
contiguous one bits, consistent with the HDLC transmission
protocol.
Each 8-bit byte recovered from WRXD will be processed for header
information, according to the protocol choice selected in
WAN_RxControl. If PPP or PPP-LEX are selected, the MSB of
the protocol2 field is checked to determine whether the frame is a
control packet or a data packet. Frames with the MSB of the
protocol field set are control packets and are forwarded to the
processor. Data packets continue on to the next stage of filtering.
Note that header encapsulation is preserved for packets destined
for the processor, and removed for packets destined for the LAN.
After determining the packet destination, the MB86976 loads
received data bytes into the receive FIFO. The receive FIFO consists
of eight 16-bit words, with control outputs to the Memory
Controller to indicate start/end of frame, frame destination
(processor, LAN, or both), and the discard of a frame already
partially or wholly transferred.
If PPP or PPP-LEX mode is selected, one bit of both of the
PPP_Protocol bytes is checked on receive. The LSbit of the
received PPP_Protocol2 field must be a zero, and the LSbit of the
PPP_Protocol1 field must be a one. If either condition does not
occur, the frame is discarded and WAN_RxErr_Cnt increments.
WAN_Reject_Frames does not increment.
The HDLC_address header field, if present, must equal FF, and the
HDLC_control field must then have a value of 03, or the WAN
frame will be rejected as a protocol error.
If present in the selected WAN mode, the LEX_FIZ0 and
LEX_MacType header fields of the WAN frame must have values
that match the corresponding MB86976 register settings, or that
frame will be rejected as a protocol error.
In parallel with frame reception, each incoming byte is used to
compute the FCS. Once the terminating flag byte is detected, the
FCS is computed by the polynomial [ x16
+ x12 + x5 + 1 ] and
checked against the constant 1D0Fh, as specified in ISO 3309, sec.
4.6.2. If the FCS comparison fails, the WAN Interface directs the
Memory Controller to discard the frame.
Also in parallel with frame reception, each incoming frame’s
length, in number of bytes, is counted. If the frame contains
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