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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 4/46頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
12
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
WAN Interface
The WAN Interface controls the transmission and reception of
frame data onto the WAN link. It supports four WAN protocols:
Compressed High-level Data Link Communication (HDLC),
HDLC, Point-to-Point (PPP) and PPP with LAN Extension
(PPP-LEX). The MB86976’s default configuration is for
Compressed HDLC communication. The WAN Interface is capable
of operating in full-duplex mode at speeds of up to 8.2 Mbps
upstream and downstream.
The WAN Interface is divided logically into receive and transmit
modules. The receive module performs four major functions. It:
1.
Recovers the physical bitstream from the WAN link, includ-
ing removal of zero insertions;
2.
Examines the packet to decode its destination (LAN, proces-
sor, or both);
3.
Removes the WAN encapsulation in accordance with the
selected WAN protocol type; and
4.
Assembles the resulting frame for transfer to the frame
buffer.
The transmit module performs analogous, but opposite functions.
It:
1.
Receives frames from the Memory Controller and buffers
them in a FIFO;
2.
Constructs the proper WAN encapsulation via configura-
tion registers and a Frame Check Sequence (FCS) generator;
3.
Performs zero insertion; and
4.
Transmits the bit stream synchronous to the external trans-
mission clock.
Configuration Registers
There are ten configuration registers which configure operation of
the WAN link. These are listed under the section headed
“Functional Control and Status Registers” on page 23.
The WAN_TxContol and WAN_RxControl registers control the
choice of protocol on the transmit and receive links, respectively.
Depending upon the protocol chosen, additional control registers
are used to perform proper data encapsulation. All registers are 8
bits in size, unless otherwise noted.
WAN Frame Formats
This table shows the Header fields in the order transmitted for each
of the possible WAN protocols. Following each field is a typical
value (in hex) that may be transmitted in this field in order for the
WAN receive port to accept a frame in that protocol. Note that the
values programmed into the PPP_Protocol1 & PPP_Protocol2
register in this table are not the default values. The default values
for these two fields must not be used. After the header fields, the
WAN frame contains (encapsulates) everything in the original
LAN frame after (but not including) the Ethernet SFD field.
Finally, after this encapsulated LAN frame, two bytes of WAN
checksum (the WAN FCS) are always appended for each protocol.
Operation
Transmission
The WAN Interface informs the Memory Controller module when
there are 4 free words in the WAN Interface transmit FIFO for a
new transmission operation. Once the Memory Controller has
identified a packet bound for WAN transmit and this signal has
been asserted, the Memory Controller begins loading the transmit
FIFO with the packet data. Transfer of additional words from the
Memory Controller to the WAN Interface transmit FIFO will
occur at the discretion of the WAN Interface, with no assumptions
on throughput or acceptable idle windows.
After the FIFO is loaded, the WAN Interface transmit logic will
transmit the appropriate header information as required by the
chosen protocol. Note that packets originating in the CPU will
WAN protocol
Header Format
Data Value
C-HDLC
< No WAN Header >
HDLC
HDLC_address
FF
HDLC_control
03
PPP
HDLC_address
FF
HDLC_control
03
PPP_Protocol2
00
PPP_Protocol1
41
PPP-LEX
HDLC_address
FF
HDLC_control
03
PPP_Protocol2
00
PPP_Protocol1
41
LEX_FIZ0
00
LEX_MacType
01
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