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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 35/46頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
40
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
FULL_JTAG_ID (JTAG Indentification. Register C0)
Lookup_Table (Lookup Table Registers 100-18Fh)
Programming the MB86976
To program the MB86976 to transmit and receive frames from the LAN interface or the WAN interface, set the following register bits.
Note:
Setting the register bits to the above configuration is the bare minimum required to transmit and receive frames to and from the LAN and WAN inter-
faces. Interrupts are not enabled. Compressed HDLC is the chosen WAN protocol. Only the control words in the Lookup Table MUST be zeroed.
UDLT Programming Examples
Source Address Filtering Example
To selectively forward frames to the WAN transmit port based on the source address field, use the following in the UDLT::
The 48 bit address takes three of the 3-word table entries, each of which must be perfectly matched.
Bit
Symbol
Type
Value
Description
32:0
JTAG_ID
R
2F00_2009h
JTAG_ID: This register contains the revision, manufacturing and production information.
Bit
Symbol
Type
Description
15:0
Lookup_Table
RW
Look-up Table: locations of the internal SRAM look-up table.
Register
Address offset
Value (hex)
Comments
MAC_Control
00
28h
Full-duplex mode enabled & Connection mode: 10Mbps.
CAM_Control
04
07h
Accept all packets.
LAN_TxControl
08
01h
Transmit enable.
LAN_RxControl
09
11h
Check the CRC and then remove it from the frame.
LAN_Opt_Set
DE
03h
LAN internal Option Set
WAN_TxControl
76
10
Compressed HDLC mode of operation, WAN transmit enabled.
WAN_RxControl
77
11h
Disable WAN FCS, Compresses HDLC mode of operation.
WAN receive enabled.
Lookup_Table
100-18Fh
00
All addresses in the lookup table, from 100h to 18Fh, should be initial-
ized to zero. On power up, they are indeterminate.
bit[15]
bit[14:10]
bit[9:8]
bit[7]
bit[6]
bit[5:3]
bit[2]
bit[1:0]
mask word
data word
enable
word offset
destination
start
stop
filter id
unused
operation
mask value
data value
1
00011
10
1
0
filter #
0
00
FFFFh
source address[47:32]
1
00100
10
0
filter #
0
00
FFFFh
source address[31:16]
1
00101
10
0
1
filter #
0
00
FFFFh
source address[15:0]
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