參數(shù)資料
型號(hào)： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 19/46頁(yè)
文件大小： 212K
代理商： MB86976PF-G
xDSL WAN Ethernet Bridge Controller
26
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
LAN Interface Register Bit Maps (Group LAN)
MAC_Control (Register 00)
The MAC control register provides global control and status information for the MAC embedded within the MB86976. The MissRoll,
CRCRoll and AlignRoll bits are status bits. All the others are control bits.
The register affects both transmission and reception. Transmit and receive can also be controlled individually. This register may be
written after power up to select customized operating features. It does not need to be written or read during normal operation.
After reset is complete, the controller clears the reset bit. Some PHYs (ethernet transceivers) may not support full duplex. Mac Loopback
overrides the full duplex bit. Some 10-Mb/s PHYs may signal LINK to indicate a different status condition. In automatic connect mode,
it will not send until there is receive activity on the 10 Mb/s interface which will then select the 10 Mb/s endec.
For MB86976 operation: The Connection mode field in this register, bits 6 and 5, must be set to 01 - Force 10Mbit/s.
CAM_Control (CAM Control. Register 04)
For MB86976 operation: Set the CAM Control register to 07 hex - Accept unicast, multicast and broadcast addresses - i.e. promiscuous
mode. The CAM referred to by this register is for an internal test condition only.
Bit
Symbol
Type
Description
0
HALT_REQ
RW0
Halt Request: Stops transmission and reception after completion of any current packets.
1
HALT_IMM
RW0
Halt Immediate: Stop transmission and reception of LAN traffic immediately.
2
RESET
RW0
Software Reset: Reset all Ethernet controller state machines and FIFOs within the MAC core of the
MB86976, (wait 2 sysclk cycles before performing any other operation).
3
FULL_DUP
RW0
Full Duplex: Allows transmission to begin while reception is occurring.
4
MAC_LOOP
RW0
MAC Loopback: Cause transmission signals to be presented as input to the receive circuit without
leaving the controller.
6:5
CONN
RW01
Connection Mode:
00= Automatic,
01=force 10-Mbit/s endec,
1X = Invalid.
7
0
N
Reserved: Unassigned.
8
AlignRoll
R0
Alignment Roll: Alignment error counter rolled over.
9
CRCRoll
R0
CRC Roll: CRC error counter rolled over.
10
MissRoll
R0
Missed error counter rolled over. (Read only)
11
EnAlignRoll
RW0
Enable Alignment Roll: Interrupt when alignment error counter rolls over.
12
EnCRCRoll
RW0
Enable CRC Roll: Interrupt when CRC error counter rolls over.
13
EnMissRoll
RW0
Enable Missed Rolled: Interrupt when missed error counter rolls over.
14
0
N
Reserved: Unassigned.
15
Link
R
Buffered signal on the LINK pin. (Read only)
Bit
Symbol
Type
Description
0
StationAcc
RW
Accept any packet with a unicast station address
1
GroupAcc
RW
Accept any packet with a multicast-group address.
2
BroadAcc
RW
Accept any packet with a broadcast address.
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