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| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 26/46頁 |
| 文件大小： | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
32
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
Processor Interface Registers (Group PROC)
Interrupt and Interrupt Mask Register
At power-up, all the interrupts are masked. The processor must write to the INTerruptMASK register to enable desired interrupts. Every
interrupt source is cleared by reading the interrupt register. Masked interrupts are asserted in the interrupt register, but not at the
interrupt pin, allowing the processor to determine the interrupt status by polling without being interrupted.
INTERRUPT (Register 40)
INTerruptMASK (Interrupt Mask. Register 42)
FrameBuffer Frame Buffer (Register 48)
The Frame Buffer is a 16 bit by 4 words deep FIFO, between the processor interface and the DRAM interface. Frames from the LAN or
the WAN, or both ports destined for the processor will transition through this Frame Buffer, and likewise, frames destined for either the
LAN or WAN, or both, ports from the processor will transition through this Frame Buffer.
Bit
Symbol
Type
Description
3:0
0
N
Reserved: Unassigned.
4
Buffer_Full
RC0
Packet was discarded due to lack of space in the Frame Buffer.
5
0
N
Reserved: Unassigned.
6
DMA_Done
RC0
DMA read/write complete
7
0
N
Reserved: Unassigned.
8
Proc_Bnd_Pkt
RC0
Processor-Bound Packet: Informs the processor that at least one packet marked for the processor is
in the Frame Buffer.
9
Proc_Buf_Full
RC0
Processor Buffer Full: Informs the processor that the buffer it wishes to write to is full.
10
Proc_Wr_Compl
RC0
Processor Write Complete: Informs the processor that the current outstanding write action has
completed, and that it may initiate another write to the Frame Buffer if necessary.
11
0
N
Reserved: Unassigned.
12
MAC_Tx_INT
R0
Mac Transmit Interrupt: MAC transmit interrupt asserted
13
MAC_Rx_INT
R0
MacTransmit Interrupt: MAC receive interrupt asserted
14
LAN_LINK_Chng
R0
LAN Link change: Asserted when the LINK pin changes states.
15
0
N
Reserved: Unassigned.
Bit
Symbol
Type
Description
15:0
INTerruptMASK
RW0
Values written into this register will mask the corresponding values written into the Interrupt Register
(Register 40).
Bit
Symbol
Type
Description
7:0
FrameBuffer
RW0
Frame Buffer : This register is the top of a 8/16 bit by 4 word deep FIFO between the CPU and
DRAM.
15:8
FrameBuffer
RW0
If BYTEWORD pin is Hi, upper byte of FrameBuffer word.
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