參數(shù)資料
型號(hào)： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 22/46頁(yè)
文件大?。?/td> 212K
代理商： MB86976PF-G
MB86976
Fujitsu Microelectronics, Inc.
29
Advanced 11/5/98
The receive status flags are set whenever the corresponding event occurs. Once set, a flag stays set until another packet arrives. In addition,
an interrupt is generated if the corresponding enable bit in the LAN_RxControl register is set, and bit 13, MacRxInterrupt, of the
INTerruptMASK, reg 42h, is clear.
A MAC receive parity error sets RxPar, if interrupt is enabled. Note that this is an internal error, and will never assert under normal con-
ditions. Software is responsible for separating alignment, CRC, and frame too long errors, and reporting them correctly as management
information. The MAC will tolerate up to a maximum of 2 bits of dribble received after an otherwise good frame. Any frame with more
dribble is an alignment error.
ALIGN_CNT (Alignment Count. Register 34)
CRC_CNT (CRC Count. Register 38)
MISS_CNT (Missed Error Count. Register 3C)
These system error count registers provide a count of packets discarded due to various types of errors. Together with status information
for packets transmitted and received, these counters provide the information needed for station management. It is the responsibility of
software to maintain a larger global count.
The missed error count register rolling over from 7FFF h to 8000 h sets the Missed Roll bit in the MAC control register. It also generates
an interrupt if the Enable Missed Roll bit is set.
If station management software wants more frequent interrupts, the missed error count register can be set to a value closer to the roll over
value of 7FFF. For example, setting the register to 7F00 would provide for an interrupt after counting 256 occurrences.
LAN_TxStatus (LAN Transmit Status. Register DC)
This register is loaded on completion of a LAN frame transmission from MAC_TxStatus (Register 0C). The bits are exactly the same as in
that register, but are retained stable until the completion of the next transmitted frame.
Bit
Symbol
Type
Description
15:0
ALIGN_CNT
RC0
The number of packets received with Alignment error. This counter increments at the end of recep-
tion if the receive block detects an Alignment error.
Bit
Symbol
Type
Description
15:0
CRC_CNT
RC0
The number of packets received with CRC errors. It increments if the receive block detects a CRC
error at the end of reception. If the received packet contains other errors, such as Alignment, this
counter does not increment.
Bit
Symbol
Type
Description
15:0
MISS_CNT
RC0
Counts the number of valid packets which are rejected by the MAC unit because the MAC receive
FIFO overflows, a parity error occurs, or the Receive Enable bit (Rx_EN) is cleared. This count
excludes packets the SADB filter rejects.
Bit
Symbol
Type
Description
15:0
LAN_TxStatus
R0
LAN Transmit Status: Loaded from MAC_TxStatus.
相關(guān)PDF資料
PDF描述
MB87033BPF SCSI BUS CONTROLLER, PQFP80
MB8867P 21.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDIP24
MB88R157A OTHER CLOCK GENERATOR, PDSO8
MB89498PMC 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PQFP100
MB89F051PMC 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86977 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
MB86977PFV-G-BND 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
MB86A21PMC-G-BNDE1 制造商:FUJITSU 功能描述:
MB86A21PMC-G-JNE1 制造商:FUJITSU 功能描述:
MB86A22PMC-ES-BNDE1 制造商:FUJITSU 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*