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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 6/46頁 |
| 文件大小： | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
14
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
more bytes than the maximum allowed size of an Ethernet frame
with maximum WAN overhead (1526 = 1518+8), the WAN
Interface signals the Memory Controller to discard the frame.
The encapsulated MAC Destination Address in frames received on
the WAN link will also be passed through the SADB filtering
engine and searched against the source address database. This
allows the WAN frames to be filtered for the MB86976 MAC
address as well as any static entries the processor may wish to add
to the database. WAN Frames sent to the CPU as a result of such
filtering will not have any WAN header information associated
with them. WAN Frames sent to the CPU will have a WAN header
only if they were directed to the CPU as a result of the MSBit set in
the PPP_Protocol2 field of a received WAN frame (when the
receive mode is set to one of the two PPP modes).
Statistics
Six registers provide statistical information regarding frame
transmission and reception. The statistics counters are read-only
and reset only at system reset. They are updated as each logged
event occurred, e.g., the byte counter is updated as each byte is
received, the frame counter is updated as each frame is received, etc.
It is the responsibility of software to maintain larger counters to
deal with overflows. These registers are described at the end of
“WAN Interface Registers (Group WAN)” on page 34.
Processor Interface
Three families of 8- and 16-bit microcontrollers are supported:
Intel 80c32, Philips P51XA-G3, and Seimens c163. To support
the variety of interfaces offered by these processors, the Processor
Interface manages processor access to the MB86976 memory
system. Commands are issued to the Processor Interface which in
turn accesses the MB86976 register space and DRAM memory
space.
The choice of processor interface is controlled by the hardwiring of
CPUSEL[1:0], and determines which of the available signals are
used and how they are interpreted by the MB86976. See table
“CPU to MB86976 Pin Mapping” on page 14 for the mapping
from each processor’s external pins to the external pins of the
MB86976.
CPU to MB86976 Pin Mapping
MB86976 Communication with processor
The processor is capable of accessing the MB86976 register space
and (indirectly) the external DRAM memory space through the
Processor Interface. No DRAM memory accesses are performed
directly by the processor; rather, it will write data and addresses
into temporary registers in the Processor Interfacein the MB86976
and internal logic will subsequently perform the memory access.
This buffering allows isolation between the distinct timing regimes
of the processor and the DRAM. By mediating memory accesses
with the Processor Interface, the MB86976 centralizes control of
all memory transactions for each of the particular processors.
The supported processors offer different size data buses. To
accommodate this difference the BYTEWORD input pin to the
MB86976 will select either byte-wide (8 bit) or word-wide (16 bit)
data. The address space on the MB86976 has been chosen to make
access to the memory simple and consistent in these two modes. All
addresses refer to byte quantities, but every 8, 16 and 32 bit
CPU Type
CPU Pin
MB86976 Pin
Intel 80c32
and similar
(MB86976
CPUSEL =
00)
Port 0(AD7:AD0)
CPD[7:0]
Latched Port 0
CPA[7:0]
Port 2 (A8)
CPA[8]
RD
CPRD
WR
CPWR
INT0 or INT1
INT
GND
BYTEWORD
Philips
P51XA-G3
(MB86976
CPUSEL =
00)
A11D7-A4D0
CPD[7:0]
A8D4 - A4D0
CPA[8:4] (latched)
A3-A0
CPA[3:0]
WR
CPWR
RD
CPRD
WAIT
READY
INT0 or INT1
INT
GND
BYTEWORD
Siemens
c163
(MB86976
CPUSEL =
01)
P0[15:0]
CPD[15:0]
P1[8:0]
CPA[8:0] (DEMUX
mode)
WR/WRL
CPWR
RD
CPRD
EX0IN-EX7IN
INT
READY
VDD
BYTEWORD
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