參數(shù)資料
型號(hào)： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 10/46頁(yè)
文件大?。?/td> 212K
代理商： MB86976PF-G
xDSL WAN Ethernet Bridge Controller
18
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
Memory Controller
Arbitration
There are 14 memory access requestors performing a total of 14
memory related operations. In addition, there are two requestors,
internal to the memory module, that request memory access
autonomously for housekeeping functions.
Processor Interface
The processor receives and transmits frames to/from the LAN or
WAN ports. In addition, the processor reads and/or writes to any
location within the DRAM address space. The Processor Interface
therefore contains four requestors: receive port, transmit port,
DMA write, and DMA read.
LAN Interface
The LAN Interface reads and writes frames into and out of the
Frame Buffer Database. The LAN Interface contains two
requestors therefore: receive port and transmit port.
WAN Interface
The WAN Interface reads and writes frames into and out of the
Frame Buffer Database. The WAN Interface contains two
requestors therefore: receive port and transmit port.
Filtering State Machine
The Filtering State Machine reads and writes Source Address
entries into and out of the Source Address Database. It contains
three requestors: LAN Destination Address filter, LAN Source
Address maintenance, and WAN Destination Address filter state
machines.
Housekeeping Functions
Housekeeping functions are performed periodically to maintain
valid memory structures. Unlike the other memory requestors, the
housekeeping functions operate autonomously and require no
intervention from external modules. The three housekeeping
requestors include the DRAM initialization, DRAM refresh, and
Source Address Database aging.
Priority
The memory arbiter prioritizes memory requests in the following
order using a round-robin scheme:
1.
LAN port frame reads/writes
2.
WAN port frame reads/writes
3.
LAN port Destination Address filtering
4.
Source Address Database maintenance
5.
WAN port Destination Address filtering
6.
Processor frame reads/writes (Processor requests can be stalled indefi-
nitely.)
7.
Processor DMA
8.
DRAM refresh
9.
Source Address Database aging (Processing may occur only during
the LAN interframe gap period.)
Filtering
A key function of the MB86976 is to minimize superfluous traffic
between any of the LAN, WAN, and Processor ports. The device
accomplishes this by filtering received frames from both the LAN
and WAN ports, determining their intended destination, and
rejecting or passing them accordingly. For example, a frame
received from the LAN port whose intended destination is also on
the LAN side of the bridge, is rejected. A frame received from the
LAN port whose intended destination is on the processor or WAN
side of the bridge is passed to the corresponding block.
Various levels of frame filtering are performed on all frames
received from both the LAN and WAN receive ports unless
configured otherwise by the corresponding control register bit(s).
In every case, frame validity is checked by the appropriate interface
first, and invalid frames (e.g. CRC failure, short frames, etc.) are
rejected as needed.
LAN Filtering
Frames received from the LAN receive port are filtered via two
mechanisms: the source address database (SADB) in the external
DRAM and the user-defined look-up table (UDLT).
Source Address Database Filtering
The source address database filtering process accomplishes three
objectives. The first is the implementation of an Ethernet bridge as
specified in the 802.1d specification. The second is to provide a
method to selectively forward or reject frames containing user-
defined destination address(es). The third is to provide a conduit
for the passage of frames from the LAN receive port to the
processor. Only one filtering operation occurs per frame. Note that
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