參數(shù)資料
型號： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 7/46頁
文件大小： 212K
代理商： MB86976PF-G
MB86976
Fujitsu Microelectronics, Inc.
15
Advanced 11/5/98
register is aligned on an even-numbered address. The memory-
mapped register layout is little endian. That is, the least significant
byte of any register always starts at an even address.
When byte-wide data is selected by a ‘0’ on the BYTEWORD pin,
the 8-bit registers are addressed directly, and the 16-bit registers as
two successively addressed bytes, with the least significant byte at
the lower address. The 32-bit registers are interpreted as four
successively addressed bytes, with the least significant byte at the
lowest address.
When word-wide databus operation is selected by a ‘1’ on the
BYTEWORD pin, and an 8-bit register needs to be addressed
alone, it will be found aligned on an even-numbered address and
the next odd-numbered (empty or padding) byte is concatenated to
form 16 bits. That is, when word-wide data is selected by
BYTEWORD, the addressed byte and the next higher byte are
chosen by a read/write transaction. While in word mode, odd-
number addresses are not allowed (i.e., the LSbit of the address of
all word-wide transactions is considered to be zero). For 8-bit
registers, the high-order byte must be ignored by software. The
16-bit registers are aligned on an even-numbered addresses and
addressed directly in word mode. The 32 bit registers can be
interpreted as two successively addressed words, with the least
significant word at the lower address.
The registers FrameBuffer and DMA_FIFO are special exceptions
to the above pattern in that their width depends on the state of
BYTEWORD. They are word-wide when the MB86976 is in word
mode, and byte-wide when it is in byte mode.
The supported processors also utilize different mechanisms for
interfacing with memory. The Intel 80c32 uses a semi-synchronous
protocol which assumes the memory device can respond to the read
or write strobe in time before the end of the cycle. The Siemens
c163 and Philips XA-G3 on the other hand, use an asynchronous
interface that waits for the addressed device, in this case the
MB86976, to assert a READY signal after each read or write
request. The Processor Interface contains separate read/write
hardware to support these two types of interfaces.
Semi-Synchronous Mode
The Intel 80c32 interfaces with external memory and peripherals
without explicit acknowledgment of bus transactions. This
restriction is not an issue for memory accesses within the MB86976
register space, as the device can respond to these transactions
within the available bus window. General accesses to the external
DRAM, however, could exceed this window during MB86976
operation if they were allowed. To address this latency mismatch
between the 80c32 and the DRAM channel on the MB86976, a
(pseudo) DMA mode is supplied for all direct processor accesses to
DRAM.
For reads and writes to the register space, the processor executes
each read/write operation individually. The Processor Interface
latches the memory transaction and decodes the address. If the
transaction is within the register space, the Processor Interface will
pass the request to the register set. Conflicts between processor
access to the register set and MB86976 updates of those registers
are settled in favor of the processor, delaying the update. Because
the register set is readily accessible, the device is able to respond to
a read transaction within the read window of the Intel 80c32.
Note that address latching must occur externally for the
multiplexed address/data bus on the 80c32 and the P51XA-G3
microcontrollers, using their ALE pin. Address latching is not
required for the C163 in demultiplexed mode. The address bits to
be latched in each case differ. The READY output will be active
during 80c32 mode transactions to allow for connection to the
P51XA-G3 WAIT pin.
Processor-DRAM pseudo-DMA operations
On receipt of a frame bound for the processor, the MB86976 loads
an 8-word buffer in the Processor Interface with the next eight
words of the frame, including the header word. Once at least four
words are resident in the buffer, the ProcessorPacket flag is set.
After polling or clearing the interrupt, the processor reads four
words from location FrameBuffer. When this FIFO becomes half
empty, the processor loads it with the next four words of the frame
and then sets the FrB_Read_GO register. The processor polls this
register until it is set, at which point the processor can retrieve the
next set of words from the local buffer. At the end of the frame, the
processor uses its knowledge of the frame length, taken from the
header word, to determine the correct total number of reads from
FrameBuffer.
To write a frame into the frame buffer for transmission on the
LAN or WAN links, the processor writes four words to location
FrameBuffer. It then writes to location FrB_Write_GO, which
allows the processor to pull the four words from the internal FIFO
and store them into the DRAM. The first word of the frame must
be the header, which specifies the size and destination of the frame.
Documentation of the header structure appears in “Frame Buffer
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