參數(shù)資料
型號(hào)： M80C286
廠商： Intel Corp.
英文描述： High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述： 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)（帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器）
文件頁(yè)數(shù)： 8/60頁(yè)
文件大?。?/td> 957K
代理商： M80C286
M80C286
Table 4. Interrupt Vector Assignments
Interrupt
Number
Related
Instructions
Does Return Address
Point to Instruction
Causing Exception
Function
Divide error exception
0
DIV, IDIV
Yes
Single step interrupt
1
All
NMI interrupt
2
INT 2 or NMI pin
Breakpoint interrupt
3
INT 3
INTO detected overflow exception
4
INTO
No
BOUND range exceeded exception
5
BOUND
Yes
Invalid opcode exception
6
Any undefined opcode
Yes
Processor extension not available exception
7
ESC or WAIT
Yes
Intel reserved–do not use
8-15
Processor extension error interrupt
16
ESC or WAIT
Intel reserved–do not use
17-31
User defined
32-255
Interrupts
An interrupt transfers execution to a new program
location. The old program address (CS:IP) and ma-
chine state (Flags) are saved on the stack to allow
resumption of the interrupted program. Interrupts fall
into three classes: hardware initiated, INT instruc-
tions, and instruction exceptions. Hardware initiated
interrupts occur in response to an external input and
are classified as non-maskable or maskable. Pro-
grams may cause an interrupt with an INT instruc-
tion. Instruction exceptions occur when an unusual
condition, which prevents further instruction pro-
cessing, is detected while attempting to execute an
instruction. The return address from an exception
will always point at the instruction causing the ex-
ception and include any leading instruction prefixes.
A table containing up to 256 pointers defines the
proper interrupt service routine for each interrupt. In-
terrupts 0–31, some of which are used for instruc-
tion exceptions, are reserved. For each interrupt, an
8-bit vector must be supplied to the M80C286 which
identifies the appropriate table entry. Exceptions
supply the interrupt vector internally. INT instructions
contain or imply the vector and allow access to all
256 interrupts. The Interrupt Vector Assignments are
listed in Table 4. Maskable hardware initiated inter-
rupts supply the 8-bit vector to the CPU during an
interrupt acknowledge bus sequence. Non-maska-
ble hardware interrupts use a predefined internally
supplied vector.
MASKABLE INTERRUPT (INTR)
The M80C286 provides a maskable hardware inter-
rupt request pin, INTR. Software enables this input
by setting the interrupt flag bit (IF) in the flag word.
All 224 user-defined interrupt sources can share this
input, yet they can retain separate interrupt han-
dlers. An 8-bit vector read by the CPU during the
interrupt acknowledge sequence (discussed in Sys-
tem Interface section) identifies the source of the
interrupt.
Further maskable interrupts are disabled while serv-
icing an interrupt by resetting the IF but as part of
the response to an interrupt or exception. The saved
flag word will reflect the enable status of the proces-
sor prior to the interrupt. Until the flag word is re-
stored to the flag register, the interrupt flag will be
zero unless specifically set. The interrupt return in-
struction includes restoring the flag word, thereby
restoring the original status of IF.
NON-MASKABLE INTERRUPT REQUEST (NMI)
A non-maskable interrupt input (NMI) is also provid-
ed. NMI has higher priority than INTR. A typical use
of NMI would be to activate a power failure routine.
The activation of this input causes an interrupt with
an internally supplied vector value of 2. No external
interrupt acknowledge sequence is performed.
While executing the NMI servicing procedure, the
M80C286 will service neither further NMI requests,
INTR requests, nor the processor extension seg-
ment overrun interrupt until an interrupt return (IRET)
instruction is executed or the CPU is reset. If NMI
occurs while currently servicing an NMI, its presence
will be saved for servicing after executing the first
IRET instruction. IF is cleared at the beginning of an
NMI interrupt to inhibit INTR interrupts.
8
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