
M80C286
271103–21
Figure 23. Basic Bus Cycle
External address latches may hold the address sta-
ble for the entire bus operation, and provide addi-
tional AC and DC buffering.
The M80C286 does not maintain the address of the
current bus operation during all T
c
states. Instead,
the address for the next bus operation may be emit-
ted during phase 2 of any T
c
. The address remains
valid during phase 1 of the first T
c
to guarantee hold
time, relative to ALE, for the address latch inputs.
Bus Control Signals
The M82C288 bus controller provides control sig-
nals; address latch enable (ALE), Read/Write com-
mands, data transmit/receive (DT/R), and data en-
able (DEN) that control the address latches, data
transceivers, write enable, and output enable for
memory and I/O systems.
The Address Latch Enable (ALE) output determines
when the address may be latched. ALE provides at
least one system CLK period of address hold time
from the end of the previous bus operation until the
address for the next bus operation appears at the
latch outputs. This address hold time is required to
support MULTIBUS and common memory systems.
The
M82C288 outputs Data Enable (DEN) and Data
Transmit/Receive (DT/R). DEN enables the data
transceivers; while DT/R controls tranceiver direc-
tion. DEN and DT/R are timed to prevent bus con-
tention between the bus master, data bus transceiv-
ers, and system data bus transceivers.
data
bus
transceivers
are
controlled
by
Command Timing Controls
Two system timing customization options, command
extension and command delay, are provided on the
M80C286 local bus.
Command extension allows additional time for exter-
nal devices to respond to a command and is analo-
gous to inserting wait states on the M8086. External
logic can control the duration of any bus operation
such that the operation is only as long as necessary.
The READY input signal can extend any bus opera-
tion for as long as necessary, see Figure 23.
Command delay allows an increase of address or
write data setup time to system bus command active
for any bus operation by delaying when the system
bus command becomes active. Command delay is
controlled by the M82C288 CMDLY input. After T
S
,
the bus controller samples CMDLY at each failing
edge of CLK. If CMDLY is HIGH, the M82C288 will
not activate the command signal. When CMDLY is
LOW, the M82C288 will activate the command sig-
nal. After the command becomes active, the CMDLY
input is not sampled.
When a command is delayed, the available re-
sponse time from command active to return read
data or accept write data is less. To customize sys-
tem bus timing, an address decoder can determine
which bus operations require delaying the com-
mand. The CMDLY input does not affect the timing
of ALE, DEN, or DT/R.
23