參數(shù)資料
型號(hào): M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
文件頁(yè)數(shù): 27/60頁(yè)
文件大?。?/td> 957K
代理商: M80C286
M80C286
271103–26
Figure 28. Back to Back Write-Write Cycles
HOLD and HLDA
HOLD AND HLDA allow another bus master to gain
control of the local bus by placing the M80C286 bus
into the T
h
state. The sequence of events required
to pass control between the M80C286 and another
local bus master are shown in Figure 29.
In this example, the M80C286 is initially in the T
h
state as signaled by HLDA being active. Upon leav-
ing T
h
, as signaled by HLDA going inactive, a write
operation is started. During the write operation an-
other local bus master requests the local bus from
the M80C286 as shown by the HOLD signal. After
completing the write operation, the M80C286 per-
forms one T
i
bus cycle, to guarantee write data hold
time, then enters T
h
as signaled by HLDA going ac-
tive.
The CMDLY signal and ARDY ready are used to
start and stop the write bus command, respectively.
Note that SRDY must be inactive or disabled by
SRDYEN to guarantee ARDY will terminate the cy-
cle.
HOLD must not be active during the time from the
leading edge of RESET until 34 CLKs following the
trailing edge of RESET.
Lock
The CPU asserts an active lock signal during Inter-
rupt-Acknowledge cycles, the XCHG instruction, and
during some descriptor accesses. Lock is also as-
serted when the LOCK prefix is used. The LOCK
prefix may be used with the following ASM-286 as-
sembly instructions; MOVS, INS, and OUTS. For bus
cycles other than Interrupt-Acknowledge cycles,
Lock will be active for the first and subsequent cy-
cles of a series of cycles to be locked. Lock will not
be shown active during the last cycle to be locked.
For the next-to-last cycle, Lock will become inactive
at the end of the first T
c
regardless of the number of
wait-states inserted. For Interrupt-Acknowledge cy-
cles, Lock will be active for each cycle, and will be-
come inactive at the end of the first T
c
for each cy-
cle regardless of the number of wait-states inserted.
Instruction Fetching
The M80C286 Bus Unit (BU) will fetch instructions
ahead of the current instruction being executed. This
activity is called prefetching. It occurs when the local
bus would otherwise be idle and obeys the following
rules:
A prefetch bus operation starts when at least two
bytes of the 6-byte prefetch queue are empty.
The prefetcher normally performs word prefetches
independent of the byte alignment of the code seg-
ment base in physical memory.
The prefetcher will perform only a byte code fetch
operation for control transfers to an instruction be-
ginning on a numerically odd physical address.
Prefetching stops whenever a control transfer or
HLT instruction is decoded by the IU and placed into
the instruction queue.
27
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