參數(shù)資料
型號: M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲管理和保護高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲器管理和保護(帶存儲管理和保護高性能16位CHMOS微處理器)
文件頁數(shù): 50/60頁
文件大?。?/td> 957K
代理商: M80C286
M80C286
271103–50
Figure 35. M80C286 Instruction Format Examples
M80C286 INSTRUCTION SET
SUMMARY
Instruction Timing Notes
The instruction clock counts listed below establish
the maximum execution rate of the M80C286. With
no delays in bus cycles, the actual clock count of an
M80C286 program will average 5% more than the
calculated clock count, due to instruction sequences
which execute faster than they can be fetched from
memory.
To calculate elapsed times for instruction se-
quences, multiply the sum of all instruction clock
counts, as listed in the table below, by the processor
clock period. A 10 MHz processor clock has a clock
period
of
100
nanoseconds
M80C286 system clock (CLK input) of 20 MHz.
and
requires
an
Instruction Clock Count Assumptions
1. The instruction has been prefetched, decoded,
and is ready for execution. Control transfer in-
struction clock counts include all time required to
fetch, decode, and prepare the next instruction for
execution.
2. Bus cycles do not require wait states.
3. There are no processor extension data transfer or
local bus HOLD requests.
4. No exceptions occur during instruction execution.
Instruction Set Summary Notes
Addressing displacements selected by the MOD
field are not shown. If necessary they appear after
the instruction fields shown.
Above/below refers to unsigned value
Greater refers to positive signed value
Less refers to less positive (more negative) signed
values
if d
e
1
if w
e
1 then word instruction; if w
e
0 then byte
instruction
if s
e
0
then 16-bit immediate data form the oper-
and
if s
e
1
then an immediate data byte is sign-ex-
tended to form the 16-bit operand
then to register; if d
e
0 then from register
x
don’t care
z
used for string primitives for comparison with
ZF FLAG
If two clock counts are given, the smaller refers to a
register operand and the larger refers to a memory
operand
*
e
add one clock if offset calculation requires
summing 3 elements
n
e
number of times repeated
m
e
number of bytes of code in next instruction
Level (L)DLexical nesting level of the procedure
50
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