
M80C286
‘‘resistive’’ type element, the associated power sup-
ply current is negligible and power dissipation is sig-
nificantly reduced when compared to the use of pas-
sive pull-up resistors.
Table 16. Bus Hold Circuitry on the M80C286
Signal
Pin
Polarity Pulled to
Location when tri-stated
S1, S0, PEACK, LOCK 4–6, 68
Hi, See Figure 33
Data Bus (D
0
–D
15
)
36–51
Hi/Lo,
See Figure 32
COD/INTA, M/IO
66–67
Hi/Lo,
See Figure 32
Pull-Up
271103–31
Figure 33. Bus Hold Circuitry Pins 4–6, 68
SYSTEM CONFIGURATIONS
The versatile bus structure of the M80C286 micro-
system, with a full complement of support chips, al-
lows flexible configuration of a wide range of sys-
tems. The basic configuration, shown in Figure 34, is
similar to an M8086 maximum mode system. It in-
cludes the CPU plus an M8259A interrupt controller,
M82C284 clock generator, and the M82C288 Bus
Controller.
As indicated by the dashed lines in Figure 34, the
ability to add processor extensions is an integral fea-
ture of M80C286 microsystems. The processor ex-
tension interface allows external hardware to per-
form special functions and transfer data concurrent
with CPU execution of other instructions. Full system
integrity is maintained because the M80C286 super-
vises all data transfers and instruction execution for
the processor extension.
The M80C287 NPX can perform numeric calcula-
tions and data transfers concurrently with CPU pro-
gram execution. Numerics code and data have the
same integrity as all other information protected by
the M80C286 protection mechanism.
The M80C286 can overlap chip select decoding and
address propagation during the data transfer for the
previous bus operation. This information is latched
by ALE during the middle of a T
s
cycle. The latched
chip select and address information remains stable
during the bus operation while the next cycle’s ad-
dress is being decoded and propagated into the sys-
tem. Decode logic can be implemented with a high
speed PROM or PAL.
The optional decode logic shown in Figure 32 takes
advantage of the overlap between address and data
of the M80C286 bus cycle to generate advanced
memory and lO-select signals. This minimizes sys-
tem performance degradation caused by address
propagation and decode delays. In addition to se-
lecting memory and I/O, the advanced selects may
be used with configurations supporting local and
system buses to enable the appropriate bus inter-
face for each bus cycle. The COD/INTA and M/IO
signals are applied to the decode logic to distinguish
between interrupt, I/O, code and data bus cycles.
By adding a bus arbiter, the M80C286 provides a
MULTIBUS system bus interface as shown in Figure
35. The ALE output of the M82C288 for the
MULTIBUS bus is connected to its CMDLY input to
delay the start of commands one system CLK as
required to meet MULTIBUS address and write data
setup times. This arrangement will add at least one
extra T
c
state to each bus operation which uses the
MULTIBUS.
A second M82C288 bus controller and additional
latches and transceivers could be added to the local
bus of Figure 35. This configuration allows the
M80C286 to support an on-board bus for local mem-
ory and peripherals, and the MULTIBUS for system
bus interfacing.
32