參數(shù)資料
型號(hào)： M80C286
廠商： Intel Corp.
英文描述： High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述： 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)（帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器）
文件頁數(shù)： 38/60頁
文件大?。?/td> 957K
代理商： M80C286
M80C286
Table 18. Pin Description
(Continued)
Symbol
Type
Name and Function
BHE
(Continued)
BHE and A0 Encodings
BHE Value
A0 Value
Function
0
0
1
1
0
1
0
1
Word transfer
Transfer on upper half of data bus (D
15
–D
8
)
Byte transfer on lower half of data bus (D
7
–D
0
)
Will never occur
S1, S0
O
BUS CYCLE STATUS
indicates initiation of a bus cycle and, along with M/IO and COD/
INTA, defines the type of bus cycle. The bus is in a T
s
state whenever one or both are LOW,
S1 and S0 are active LOW and float to 3-state OFF
*
during bus hold acknowledge.
M80C286 Bus Cycle Status Definition
COD/INTA
M/IO
S1
S0
Bus Cycle Initiated
0 (LOW)
0
0
0
0
0
0
0
1 (HIGH)
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt acknowledge
Will not occur
Will not occur
None; not a status cycle
IF A1
e
1 then halt; else shutdown
Memory data read
Memory data write
None; not a status cycle
Will not occur
I/O read
I/O write
None; not a status cycle
Will not occur
Memory instruction read
Will not occur
None; not a status cycle
M/IO
O
MEMORY I/O SELECT
distinguishes memory access from I/O access. If HIGH during T
s
, a
memory cycle or a halt/shutdown cycle is in progress. If LOW, an I/O cycle or an interrupt
acknowledge cycle is in progress. M/IO floats to 3-state OFF
*
during bus hold
acknowledge.
COD/INTA
O
CODE/INTERRUPT ACKNOWLEDGE
distinguishes instruction fetch cycles from memory
data read cycles. Also distinguishes interrupt acknowledge cycles from I/O cycles. COD/
INTA floats to 3-state OFF
*
during bus hold acknowledge. Its timing is the same as M/IO.
LOCK
O
BUS LOCK
indicates that other system bus masters are not to gain control of the system
bus for the current and the following bus cycle. The LOCK signal may be activated explicitly
by the ‘‘LOCK’’ instruction prefix or automatically by M80C286 hardware during memory
XCHG instructions, interrupt acknowledge, or descriptor table access. LOCK is active LOW
and floats to 3-state OFF
*
during bus hold acknowledge.
READY
I
BUS READY
terminates a bus cycle. Bus cycles are extended without limit until terminated
by READY LOW. READY is an active LOW synchronous input requiring setup and hold
times relative to the system clock be met for correct operation. READY is ignored during
bus hold acknowledge.
HOLD
HLDA
I
BUS HOLD REQUEST AND HOLD ACKNOWLEDGE
control ownership of the M80C286
local bus. The HOLD input allows another local bus master to request control of the local
bus. When control is granted, the M80C286 will float its bus drivers to 3-state OFF
*
and
then activate HLDA, thus entering the bus hold acknowledge condition. The local bus will
remain granted to the requesting master until HOLD becomes inactive which results in the
M80C286 deactivating HLDA and regaining control of the local bus. This terminates the bus
hold acknowledge condition. HOLD may be asynchronous to the system clock. These
signals are active HIGH.
O
INTR
I
INTERRUPT REQUEST
requests the M80C286 to suspend its current program execution
and service a pending external request. Interrupt requests are masked whenever the
interrupt enable bit in the flag word is cleared. When the M80C286 responds to an interrupt
request, it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt vector
that identifies the source of the interrupt. To assure program interruption, INTR must remain
active until the first interrupt acknowledge cycle is completed. INTR is sampled at the
beginning of each processor cycle and must be active HIGH at least two processor cycles
before the current instruction ends in order to interrupt before the next instruction. INTR is
level sensitive, active HIGH, and may be asynchronous to the system clock.
*
See bus hold circuitry section.
38
相關(guān)PDF資料
PDF描述
M80C287 80-Bit CHMOS III Numeric Processor Exetension(80位CHMOS III數(shù)字處理器擴(kuò)展)
M80C51FB CHMOS Single-Chip 8-Bit Microcontroller(CHMOS單芯片8位微控制器)
M80C86 CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器)
M80C86-20 CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器)
M80C86-2 16-BIT CHMOS MICROPROCESSOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M80C287 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION
M80C31BH 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
M80C31F 制造商:OK International 功能描述:
M80C31FV-1 制造商:OKI Semiconductor 功能描述:8-BIT, 16 MHZ, MICROCONTROLLER, PQFP44
M80C39H 制造商:OK International 功能描述:Electronic Component
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*