
M80C286
271103–2
Figure 3. Status and Control Register Bit Functions
Flags Word Description
The Flags word (Flags) records specific characteris-
tics of the result of logical and arithmetic instructions
(bits 0, 2, 4, 6, 7, and 11) and controls the operation
of the M80C286 within a given operating mode (bits
8 and 9). Flags is a 16-bit register. The function of
the flag bits is given in Table 1.
Instruction Set
The instruction set is divided into seven categories:
data transfer, arithmetic, shift/rotate/logical, string
manipulation, control transfer, high level instruc-
tions, and processor control. These categories are
summarized in Table 2.
An M80C286 instruction can reference zero, one, or
two operands; where an operand resides in a regis-
ter, in the instruction itself, or in memory. Zero-oper-
and instructions (e.g. NOP and HLT) are usually one
byte long. One-operand instructions (e.g. INC and
DEC) are usually two bytes long but some are en-
coded in only one byte. One-operand instructions
may reference a register or memory location. Two-
operand instructions permit the following six types of
instruction operations:
DRegister to Register
DMemory to Register
DImmediate to Register
DMemory to Memory
DRegister to Memory
DImmediate to Memory
Table 1. Flags Word Bit Functions
Bit
Name
Function
Position
0
CF
Carry FlagDSet on high-order bit
carry or borrow; cleared otherwise
2
PF
Parity FlagDSet if low-order 8 bits
of result contain an even number of
1-bits; cleared otherwise
4
AF
Set on carry from or borrow to the
low order four bits of AL; cleared
otherwise
6
ZF
Zero FlagDSet if result is zero;
cleared otherwise
7
SF
Sign FlagDSet equal to high-order
bit of result (0 if positive, 1 if negative)
11
OF
Overflow FlagDSet if result is a too-
large positive number or a too-small
negative number (excluding sign-bit)
to fit in destination operand; cleared
otherwise
8
TF
Single Step FlagDOnce set, a sin-
gle step interrupt occurs after the
next instruction executes. TF is
cleared by the single step interrupt.
9
IF
Interrupt-enable FlagDWhen set,
maskable interrupts will cause the
CPU to transfer control to an inter-
rupt vector specified location.
10
DF
Direction FlagDCauses string
instructions to auto decrement
the appropriate index registers
when set. Clearing DF causes
auto increment.
3