參數(shù)資料
型號: M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲管理和保護高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲器管理和保護(帶存儲管理和保護高性能16位CHMOS微處理器)
文件頁數(shù): 12/60頁
文件大?。?/td> 957K
代理商: M80C286
M80C286
from the tables in memory. The 16-bit offset is add-
ed to the segment base address to form the physical
address as shown in Figure 10. The tables are auto-
matically referenced by the CPU whenever a seg-
ment register is loaded with a selector. All M80C286
instructions which load a segment register will refer-
ence the memory based tables without additional
software. The memory based tables contain 8 byte
values called descriptors.
271103–8
Figure 9. Protected Mode Memory Addressing
DESCRIPTORS
Descriptors define the use of memory. Special types
of descriptors also define new functions for transfer
of control and task switching. The M80C286 has
segment descriptors for code, stack and data seg-
ments, and system control descriptors for special
system data segments and control transfer opera-
tions, see Figure 10. Descriptor accesses are per-
formed as locked bus operations to assure descrip-
tor integrity in multi-processor systems.
CODE AND DATA SEGMENT DESCRIPTORS
(S
e
1)
Besides segment base addresses, code and data
descriptors contain other segment attributes includ-
ing segment size (1 to 64K bytes), access rights
(read only, read/write, execute only, and execute/
read), and presence in memory (for virtual memory
systems) (See Figure 11). Any segment usage vio-
lating a segment attribute indicated by the segment
descriptor will prevent the memory cycle and cause
an exception or interrupt.
271103–9
*
Must be set to 0 for compatibility with 80386.
Figure 10. Code or Data Segment Descriptor
Access Rights Byte Definition
Bit
Name
Function
Position
7
Present (P)
P
e
1
P
e
0
Segment is mapped into physical memory.
No mapping to physical memory exits, base and limit are
not used.
Segment privilege attribute used in privilege tests.
6–5
Descriptor Privilege
Level (DPL)
Segment Descrip-
tor (S)
4
S
e
1
S
e
0
E
e
0
ED
e
0
ED
e
1
W
e
0
W
e
1
E
e
1
C
e
1
Code or Data (includes stacks) segment descriptor
System Segment Descriptor or Gate Descriptor
3
2
Executable (E)
Expansion Direc-
tion (ED)
Writeable (W)
Data segment descriptor type is:
Expand up segment, offsets must be
s
limit.
Expand down segment, offsets must be
l
limit.
Data segment may not be written into.
Data segment may be written into.
If
Data
Segment
(S
e
1,
E
e
0)
If
Code
Segment
1
Type
Field
Definition
3
2
Executable (E)
Conforming (C)
Code Segment Descriptor type is:
Code segment may only be executed
when CPL
t
DPL and CPL
remains unchanged.
Code segment may not be read
Code segment may be read.
1
Readable (R)
R
e
0
R
e
1
A
e
0
A
e
1
(S
e
1,
E
e
1)
*
0
Accessed (A)
Segment has not been accessed.
Segment selector has been loaded into segment register
or used by selector test instructions.
Figure 11. Code and Data Segment Descriptor Formats
12
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