參數(shù)資料
型號: M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲管理和保護高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲器管理和保護(帶存儲管理和保護高性能16位CHMOS微處理器)
文件頁數(shù): 31/60頁
文件大?。?/td> 957K
代理商: M80C286
M80C286
271103–29
Figure 31. Example Power-Down Sequence
THE POWER-DOWN FEATURE OF
THE M80C286
The M80C286, unlike the HMOS part, can enter into
a power-down mode. By stopping the processor
CLK, the processor will enter a power-down mode.
Once in the power-down mode, all M80C286 outputs
remain static (the same state as before the mode
was entered). The M80C286 D.C. specification I
CCS
rates the amount of current drawn by the processor
when in the power-down mode. When the CLK is
reapplied to the processor, it will resume execution
where it was interrupted.
In order to obtain maximum benefits from the power-
down mode, certain precautions should be taken.
When in the power-down mode, all M80C286 out-
puts remain static and any output that is turned on
and remains in a HIGH condition will source current
when loaded. Best low-power performance can be
obtained by first putting the processor in the HOLD
condition (turning off all of the output buffers), and
then stopping the processor CLK in the phase 2
state. In this condition, any output that is loaded will
source only the ‘‘Bus Hold Sustaining Current’’.
When stopping the processor clock, minimum clock
high and low times cannot be violated (no glitches
on the clock line).
Violating this condition can cause the M80C286 to
erase its internal register states. Note that all inputs
to the M80C286 (CLK, HOLD, PEREQ, RESET,
READY, INTR, NMI, BUSY, and ERROR) should be
at V
CC
or V
SS
; any other value will cause the
M80C286 to draw additional current.
When coming out of power-down mode, the system
CLK must be started with the same polarity in which
it was stopped. An example power down sequence
is shown in Figure 31.
BUS HOLD CIRCUITRY
To avoid high current conditions caused by floating
inputs to peripheral CMOS devices and eliminate the
need for pull-up/down resistors, ‘‘bus-hold’’ circuitry
has been used on all tri-state M80C286 outputs. See
Table 16 for a list of these pins and Figures 32 and
33 for a complete description of which pins have bus
hold circuitry. These circuits will maintain the last
valid logic state if no driving source is present (i.e.,
an unconnected pin or a driving source which goes
to a high impedance state). To overdrive the ‘‘bus
hold’’ circuits, an external driver must be capable of
supplying the maximum ‘‘Bus Hold Overdrive’’ sink
or source current at valid input voltage levels. Since
this ‘‘bus hold’’ circuitry is active and not a
Pull-Up/Pull-Down
271103–30
Figure 32. Bus Hold Circuitry Pins 36–51, 66–67
31
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相關代理商/技術參數(shù)
參數(shù)描述
M80C287 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION
M80C31BH 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
M80C31F 制造商:OK International 功能描述:
M80C31FV-1 制造商:OKI Semiconductor 功能描述:8-BIT, 16 MHZ, MICROCONTROLLER, PQFP44
M80C39H 制造商:OK International 功能描述:Electronic Component