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參數(shù)資料
| 型號： | M80C286 |
| 廠商： | Intel Corp. |
| 英文描述： | High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲管理和保護(hù)高性能16位CHMOS微處理器) |
| 中文描述： | 高性能CHMOS微處理器存儲器管理和保護(hù)（帶存儲管理和保護(hù)高性能16位CHMOS微處理器） |
| 文件頁數(shù)： | 18/60頁 |
| 文件大小： | 957K |
| 代理商： | M80C286 |
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M80C286
PRIVILEGE LEVEL CHANGES
Any control transfer that changes CPL within the
task, causes a change of stacks as part of the oper-
ation. Initial values of SS:SP for privilege levels 0, 1,
and 2 are kept in the task state segment (refer to
Task Switch Operation). During a JMP or CALL con-
trol transfer, the new stack pointer is loaded into the
SS and SP registers and the previous stack pointer
is pushed onto the new stack.
When returning to the original privilege level, its
stack is restored as part of the RET or IRET instruc-
tion operation. For subroutine calls that pass param-
eters on the stack and cross privilege levels, a fixed
number of words, as specified in the gate, are cop-
ied from the previous stack to the current stack. The
inter-segment RET instruction with a stack adjust-
ment value will correctly restore the previous stack
pointer upon return.
Protection
The M80C286 includes mechanisms to protect crit-
ical instructions that affect the CPU execution state
(e.g. HLT) and code or data segments from improper
usage. These protection mechanisms are grouped
into three forms:
Restricted usage of segments (e.g. no write al-
lowed to read-only data segments). The only seg-
ments available for use are defined by descrip-
tors in the Local Descriptor Table (LDT) and
Global Descriptor Table (GDT).
Restricted access to segments via the rules of
privilege and descriptor usage.
Privileged instructions or operations that may
only be executed at certain privilege levels as de-
termined by the CPL and I/O Privilege Level
(IOPL). The IOPL is defined by bits 14 and 13 of
the flag word.
These checks are performed for all instructions and
can be split into three categories: segment load
checks (Table 11), operand reference checks (Table
12), and privileged instruction checks (Table 13).
Any violation of the rules shown will result in an ex-
ception. A not-present exception related to the stack
segment causes exception 12.
The IRET and POPF instructions do not perform
some of their defined functions if CPL is not of suffi-
cient privilege (numerically small enough). Precisely
these are:
#
The IF bit is not changed if CPL
l
IOPL.
#
The IOPL field of the flag word is not changed if
CPL
l
0.
No exceptions or other indication are given when
these conditions occur.
Table 11. Segment Register Load Checks
Error Description
Exception
Number
Descriptor table limit exceeded
13
Segment descriptor not-present
11 or 12
Privilege rules violated
13
Invalid descriptor/segment type seg-
ment register load:
DRead only data segment load to
SS
DSpecial Control descriptor load to
DS, ES, SS
DExecute only segment load to
DS, ES, SS
DData segment load to CS
DRead/Execute code segment
load to SS
13
Table 12. Operand Reference Checks
Error Description
Exception
Number
Write into code segment
Read from execute-only code
segment
Write to read-only data segment
Segment limit exceeded
1
13
13
13
12 or 13
NOTE:
Carry out in offset calculations is ignored.
Table 13. Privileged Instruction Checks
Error Description
Exception
Number
CPL
i
0 when executing the following
instructions:
LIDT, LLDT, LGDT, LTR, LMSW,
CTS, HLT
CPL
l
IOPL when executing the fol-
lowing instructions:
INS, IN, OUTS, OUT, STI, CLI,
LOCK
13
13
EXCEPTIONS
The M80C286 detects several types of exceptions
and interrupts, in protected mode (see Table 14).
Most are restartable after the exceptional condition
is removed. Interrupt handlers for most exceptions
can read an error code, pushed on the stack after
the return address, that identifies the selector in-
volved (0 if none). The return address normally
points to the failing instruction, including all leading
prefixes. For a processor extension segment over-
run exception, the return address will not point at the
ESC instruction that caused the exception; however,
the processor extension registers may contain the
address of the failing instruction.
18
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PDF描述 |
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| M80C287 | 80-Bit CHMOS III Numeric Processor Exetension(80位CHMOS III數(shù)字處理器擴(kuò)展) |
| M80C51FB | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS單芯片8位微控制器) |
| M80C86 | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| M80C86-20 | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| M80C86-2 | 16-BIT CHMOS MICROPROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M80C287 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION |
| M80C31BH | 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space |
| M80C31F | 制造商:OK International 功能描述: |
| M80C31FV-1 | 制造商:OKI Semiconductor 功能描述:8-BIT, 16 MHZ, MICROCONTROLLER, PQFP44 |
| M80C39H | 制造商:OK International 功能描述:Electronic Component |
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