參數(shù)資料
型號(hào): M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
文件頁(yè)數(shù): 51/60頁(yè)
文件大?。?/td> 957K
代理商: M80C286
M80C286
The following comments describe possible excep-
tions, side effects, and allowed usage for instruc-
tions in both operating modes of the M80C286.
REAL ADDRESS MODE ONLY
1. This is a protected mode instruction. Attempted
execution in real address mode will result in an
undefined opcode exception (6).
2. A segment overrun exception (13) will occur if a
word operand reference at offset FFFF(H) is at-
tempted.
3. This instruction may be executed in real address
mode to initialize the CPU for protected mode.
4. The IOPL and NT fields will remain 0.
5. Processor extension segment overrun interrupt
(9) will occur if the operand exceeds the seg-
ment limit.
EITHER MODE
6. An exception may occur, depending on the value
of the operand.
7. LOCK is automatically asserted regardless of the
presence or absence of the LOCK instruction
prefix.
8. LOCK does not remain active between all oper-
and transfers.
PROTECTED VIRTUAL ADDRESS MODE ONLY
9. A general protection exception (13) will occur if
the memory operand cannot be used due to ei-
ther a segment limit or access rights violation. If
a stack segment limit is violated, a stack seg-
ment overrun exception (12) occurs.
10. For segment load operations, the CPL, RPL, and
DPL must agree with privilege rules to avoid an
exception. The segment must be present to
avoid a not-present exception (11). If the SS reg-
ister is the destination, and a segment not-pres-
ent violation occurs, a stack exception (12) oc-
curs.
11. All segment descriptor accesses in the GDT or
LDT made by this instruction will automatically
assert LOCK to maintain descriptor integrity in
multiprocessor systems.
12. JMP, CALL, INT, RET, IRET instructions refer-
ring to another code segment will cause a gener-
al protection exception (13) if any privilege rule is
violated.
13. A general protection exception (13) occurs if
CPL
i
0.
14. A general protection exception (13) occurs if
CPL
l
IOPL.
15. The IF field of the flag word is not updated if CPL
l
IOPL. The IOPL field is updated only if
CPL
e
0.
16. Any violation of privilege rules as applied to the
selector operand do not cause a protection ex-
ception; rather, the instruction does not return a
result and the zero flag is cleared.
17. If the starting address of the memory operand
violates a segment limit, or an invalid access is
attempted, a general protection exception (13)
will occur before the ESC instruction is execut-
ed. A stack segment overrun exception (12) will
occur if the stack limit is violated by the oper-
and’s starting address. If a segment limit is vio-
lated during an attempted data transfer then a
processor extension segment overrun exception
(9) occurs.
18. The destination of an INT, JMP, CALL, RET or
IRET instruction must be in the defined limit of a
code segment or a general protection exception
(13) will occur.
51
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