參數(shù)資料
型號(hào): M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
文件頁(yè)數(shù): 42/60頁(yè)
文件大小: 957K
代理商: M80C286
M80C286
A.C. CHARACTERISTICS
Over Specified Operating Conditions
A.C. timings are referenced to 1.5V points of signals as illustrated in datasheet waveforms, unless otherwise
noted.
Symbol
Parameter
10 MHz
Unit
Comments
Min
Max
1
System Clock (CLK) Period
50
DC
ns
2
System Clock (CLK) LOW Time
12
ns
at 1.0V
3
System Clock (CLK) HIGH Time
16
ns
at 3.6V
17
System Clock (CLK) Rise Time
8
ns
1.0V to 3.6V
18
System Clock (CLK) Fall Time
8
ns
3.6V to 1.0V
4
Asynchronous Inputs Setup Time
20
ns
(Note 1)
5
Asynchronous Inputs Hold Time
20
ns
(Note 1)
6
RESET Setup Time
23
ns
7
RESET Hold Time
5
ns
8
Read Data Setup Time
8
ns
9
Read Data Hold Time
8
ns
10
READY Setup Time
26
ns
11
READY Hold Time
25
ns
12a1
Status Active Delay
5
22
ns
(Notes 2, 3)
12a2
PEACK Active Delay
5
22
ns
(Notes 2, 3)
12b
Status/PEACK Inactive Delay
3
30
ns
(Notes 2, 3)
13
Address Valid Delay
4
35
ns
(Notes 2, 3)
14
Write Data Valid Delay
3
40
ns
(Notes 2, 3)
15
Address/Status/Data Float Delay
2
47
ns
(Notes 2, 4)
16
HLDA Valid Delay
3
47
ns
(Notes 2, 3)
19
Address Valid To Status
Valid Setup Time
27
ns
(Notes 2, 3)
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing
purposes, to assure recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK, to 1.5V or float on the output as appropriate for valid or floating condition.
3. Output load: C
L
e
100 pF.
4. Float condition occurs when output current is less than I
LO
in magnitude.
42
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