參數(shù)資料
型號(hào): M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
文件頁(yè)數(shù): 24/60頁(yè)
文件大?。?/td> 957K
代理商: M80C286
M80C286
271103–22
Figure 24. CMDLY Controls the Leading Edge of Command Signal
Figure 24 illustrates four uses of CMDLY. Example 1
shows delaying the read command two system
CLKs for cycle N-1 and no delay for cycle N, and
example 2 shows delaying the read command one
system CLK for cycle N-1 and one system CLK de-
lay for cycle N.
Bus Cycle Termination
At maximum transfer rates, the M80C286 bus alter-
nates between the status and command states. The
bus status signals become inactive after T
s
so that
they may correctly signal the start of the next bus
operation after the completion of the current cycle.
No external indication of T
c
exists on the M80C286
local bus. The bus master and bus controller enter
T
c
directly after T
s
and continue executing T
c
cycles
until terminated by READY.
READY Operation
The current bus master and M82C288 bus controller
terminate each bus operation simultaneously to
achieve maximum bus operation bandwidth. Both
are informed in advance by READY active (open-
collector output from M82C284) which identifies the
last T
C
cycle of the current bus operation. The bus
master and bus controller must see the same sense
of the READY signal, thereby requiring READY be
synchronous to the system clock.
Synchronous Ready
The M82C284 clock generator provides READY
synchronization from both synchronous and asyn-
chronous sources (see Figure 25). The synchronous
ready input (SRDY) of the clock generator is sam-
pled with the falling edge of CLK at the end of phase
1 of each T
c
. The state of SRDY is then broadcast to
the bus master and bus controller via the READY
output line.
Asynchronous Ready
Many systems have devices or subsystems that are
asynchronous to the system clock. As a result, their
ready outputs cannot be guaranteed to meet the
M82C284 SRDY setup and hold time requirements.
But the M82C284 asynchronous ready input (ARDY)
is designed to accept such signals. The ARDY input
is sampled at the beginning of each T
C
cycle by
M82C284 synchronization logic. This provides one
system CLK cycle time to resolve its value before
broadcasting it to the bus master and bus controller.
24
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