參數(shù)資料
型號: M80C286
廠商: Intel Corp.
英文描述: High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
中文描述: 高性能CHMOS微處理器存儲(chǔ)器管理和保護(hù)(帶存儲(chǔ)管理和保護(hù)高性能16位CHMOS微處理器)
文件頁數(shù): 14/60頁
文件大小: 957K
代理商: M80C286
M80C286
Gate Descriptor
271103–11
*
Must be set to 0 for compatibility with 80386 (X is don’t care)
Gate Descriptor Fields
Name
Value
Description
4
5
6
7
–Call Gate
–Task Gate
–Interrupt Gate
–Trap Gate
TYPE
P
0
–Descriptor Contents are not
valid
–Descriptor Contents are
valid
1
DPL
0–3
Descriptor Privilege Level
WORD
COUNT
Number of words to copy
from callers stack to called
procedures stack. Only used
with call gate.
0–31
Selector to the target code
segment (Call, Interrupt or
Trap Gate)
Selector to the target task
state segment (Task Gate)
DESTINATION
SELECTOR
16-bit
selector
DESTINATION
OFFSET
16-bit
offset
Entry point within the target
code segment
Figure 13. Gate Descriptor Format
Exception 13 is generated when the gate is used if a
destination selector does not refer to the correct de-
scriptor type. The word count field is used in the call
gate descriptor to indicate the number of parameters
(0–31 words) to be automatically copied from the
caller’s stack to the stack of the called routine when
a control transfer changes privilege levels. The word
count field is not used by any other gate descriptor.
The access byte format is the same for all gate de-
scriptors. P
e
1 indicates that the gate contents are
valid. P
e
0 indicates the contents are not valid and
causes exception 11 if referenced. DPL is the de-
scriptor privilege level and specifies when this de-
scriptor may be used by a task (refer to privilege
discussion below). Bit 4 must equal 0 to indicate a
system control descriptor. The
TYPE
field specifies
the descriptor type as indicated in Figure 13.
SEGMENT DESCRIPTOR CACHE REGISTERS
A segment descriptor cache register is assigned to
each of the four segment registers (CS, SS, DS, ES).
Segment
descriptors
are
(cached) into a segment descriptor cache register
(Figure 14) whenever the associated segment regis-
ter is loaded with a selector. Only segment descrip-
tors may be loaded into segment descriptor cache
registers. Once loaded, all references to that seg-
ment of memory use the cached descriptor informa-
tion instead of reaccessing the descriptor. The de-
scriptor cache registers are not visible to programs.
No instructions exist to store their contents. They
only change when a segment register is loaded.
automatically
loaded
SELECTOR FIELDS
A protected mode selector has three fields: descrip-
tor entry index, local or global descriptor table indi-
cator (TI), and selector privilege (RPL) as shown in
Figure 15. These fields select one of two memory
based tables of descriptors, select the appropriate
table entry and allow highspeed testing of the selec-
tor’s privilege attribute (refer to privilege discussion
below).
271103–12
Figure 15. Selector Fields
271103–13
Figure 14. Descriptor Cache Registers
14
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