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| 型號： | M80C286 |
| 廠商： | Intel Corp. |
| 英文描述： | High Performance CHMOS Microprocessor With Memory Management And Protection(帶存儲管理和保護(hù)高性能16位CHMOS微處理器) |
| 中文描述： | 高性能CHMOS微處理器存儲器管理和保護(hù)（帶存儲管理和保護(hù)高性能16位CHMOS微處理器） |
| 文件頁數(shù)： | 37/60頁 |
| 文件大?。?/td> | 957K |
| 代理商： | M80C286 |
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M80C286
Table 17. Pin Cross Reference for M80C286
Signal
CQFP
PGA
A0
44
34
A1
45
33
A2
46
32
A3
50
28
A4
51
27
A5
52
26
A6
53
25
A7
54
24
A8
55
23
A9
56
22
A10
57
21
A11
58
20
A12
59
19
A13
60
18
A14
61
17
A15
62
16
A16
63
15
A17
64
14
A18
65
13
A19
66
12
A20
67
11
A21
68
10
A22
2
8
Signal
CQFP
PGA
A23
3
7
D0
42
36
D1
40
38
D2
38
40
D3
36
42
D4
34
44
D5
32
46
D6
30
48
D7
28
50
D8
41
37
D9
39
39
D10
37
41
D11
35
43
D12
33
45
D13
31
47
D14
29
49
D15
27
51
CLK
47
31
RESET
49
29
BHE
9
1
S1
6
4
S0
5
5
PEACK
4
6
Signal
CQFP
PGA
LOCK
10
68
M/IO
11
67
COD/INTA
12
66
HLDA
13
65
HOLD
14
64
READY
15
63
PEREQ
17
61
NMI
19
59
INTR
21
57
BUSY
24
54
ERROR
25
53
CAP
26
52
V
SS
1
9
V
SS
18
35
V
SS
43
60
V
CC
16
30
V
CC
48
62
N.C.
7
2
N.C.
8
3
N.C.
20
55
N.C.
22
56
N.C.
23
58
Table 18. Pin Description
The following pin function descriptions are for the M80C286 microprocessor :
Symbol
Type
Name and Function
CLK
I
SYSTEM CLOCK
provides the fundamental timing for M80C286 systems. It is
divided by two inside the M80C286 to generate the processor clock. The internal
divide-by-two circuitry can be synchronized to an external clock generator by a
LOW to HIGH transition on the RESET input.
D
15
–D
0
I/O
DATA BUS
inputs data during memory, I/O, and interrupt acknowledge read
cycles; outputs data during memory and I/O write cycles. The data bus is active
HIGH and floats to 3-state OFF
*
during bus hold acknowledge.
A
23
–A
0
O
ADDRESS BUS
outputs physical memory and I/O port addresses. A0 is LOW
when data is to be transferred on pins D
7–0
. A
23
–A
16
are LOW during I/O
transfers. The address bus is active HIGH and floats to 3-state OFF
*
during bus
hold acknowledge.
BHE
O
BUS HIGH ENABLE
indicates transfer or data on the upper byte of the data bus.
D
15–8
. Eight-bit oriented devices assigned to the upper byte of the data bus would
normally use BHE to condition chip select functions. BHE is active LOW and floats
to 3-state OFF
*
during bus hold acknowledge.
*
See bus hold circuitry section.
37
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M80C287 | 80-Bit CHMOS III Numeric Processor Exetension(80位CHMOS III數(shù)字處理器擴(kuò)展) |
| M80C51FB | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS單芯片8位微控制器) |
| M80C86 | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| M80C86-20 | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| M80C86-2 | 16-BIT CHMOS MICROPROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M80C287 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80-BIT CHMOS III NUMERIC PROCESSOR EXTENSION |
| M80C31BH | 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space |
| M80C31F | 制造商:OK International 功能描述: |
| M80C31FV-1 | 制造商:OKI Semiconductor 功能描述:8-BIT, 16 MHZ, MICROCONTROLLER, PQFP44 |
| M80C39H | 制造商:OK International 功能描述:Electronic Component |
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