參數(shù)資料
型號(hào)： M44C588
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER
文件頁(yè)數(shù)： 7/44頁(yè)
文件大小： 549K
代理商： M44C588
M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
15 (44)
System Configuration Register (SC)
Primary register address: ’E’hex
Bit 3
Bit 2
Bit 1
Bit 0
SC: write
RC1
RC0
OS1
OS0
Reset value: 1111b
RC1, RC0
Internal RC oscillator 1 frequency select (SYSCLmax)
RC1
RC0
SYSCLmax @ 25
°C, VDD = 5 V
Note
0
0
7.5 MHz
0
1
3.2 MHz
1
0
2.0 MHz
1
1
0.8 MHz
Reset value
OS1, OS0
Oscillator selection bits (in conjunction with the CCS-bit)
CCS
OS1
OS0
SUBCL
System Oscillator Selection
0
1
1
External input clock at SCLIN
0
0
1
SYSCLmax/64
RC-oscillator 2 with Rext
0
1
0
4-MHz crystal oscillator
0
0
0
32 kHz
32-kHz crystal oscillator
1
x
x
SYSCLmax/64 or 32 kHz
RC-oscillator 1
If CCS = 0 in the CM-register, the RC-oscillator 1 is stopped.
1.5.4
Power-down Modes
The sleep mode is a shut-down condition which is used to
reduce the average system power consumption in applica-
tions where the
C is not fully utilized. In this mode, the
system clock is stopped. During the sleep mode the pe-
ripheral modules remain active and are able to generate
interrupts. The
C exits the sleep mode by carrying out
any interrupt or a reset condition.
The sleep mode can only be kept when none of the inter-
rupt pending or active register bits are set. The application
of the $AUTOSLEEP routine ensures the correct function
of the sleep mode.
The total power consumption is directly proportional to
the active time of the
C. For a rough estimation of the
expected average system current consumption, the fol-
lowing formula should be used:
Itotal (VDD,fsyscl) = ISleep + (IDD
Tactive / Ttotal)
IDD depends on VDD and fsyscl.
The M44C588 has various power-down modes. During
the sleep mode the clock for the MARC4 core is stopped.
With the NSTOP-bit in the clock management register
(CM) it is programmable if the clock for the on–chip pe-
ripherals is active or stopped during the sleep mode. If the
clock for the core and the peripherals is stopped the se-
lected oscillator is switched off. An exception is the
32-kHz oscillator, if it is selected it runs continously inde-
pendent on the NSTOP-bit. If the oscillator is stopped or
the 32 kHz oscillator is selected, power consumption is
extremely reduced.
Table 5. Power-down modes
Mode
CPU Core
NSTOP
RC-Oscillator 1
RC-Oscillator 2
4-MHz Oscillator
32-kHz Oscillator
External Input
Clock at SCLIN
Active
RUN
1
RUN
RUN
Enabled
Power-down
SLEEP
1
RUN
RUN
Enabled
SLEEP
SLEEP
0
STOP
RUN
Disabled
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