參數(shù)資料
型號(hào)： M44C588
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER
文件頁(yè)數(shù)： 19/44頁(yè)
文件大小： 549K
代理商： M44C588
M44C588
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
Preliminary Information
26 (44)
2.5
Bidirectional Port 4
Master reset
Q
V
DD
V
DD
BP4y
Mask options
*
P4DATy
I/O Bus
D
I/O Bus
*
Pull-up
Pull-down
(Data out)
*
S
14012
P4DATy
S
Q
D
TCIOy
TOut
(Direction)
TDir
TIn
V
DD
*
Static
pull-up
*
V
DD
Static
pull-down
Figure 23. Bidirectional Port 4
The bidirectional Port 4 is both a bitwise configurable I/O
port and provides the external pins for both the Timer 0
and the Timer 1. As a normal port, it performs in exactly
the same way as bidirectional port type 2 (see figure 14).
Two additional multiplexers allow data and port direction
control to be passed over to other internal modules
(Timer 0 or Timer 1). Each of the four Port 4 pins can be
individually switched by the Timer/Counter I/O Register
(TCIO). Figure 23 shows the internal interfaces to Port 4.
2.6
Interval Timers / Prescaler
The interval timers are based on a frequency divider for
generating two independent time base interrupts. It is
driven by SUBCL generated by the clock module (see
figure 10) and consists of a 15-stage binary divider and
two programmable multiplexers for selecting the ap-
propriate interrupt frequencies for each interrupt source
(see figure 24). Each multiplexer is completely indepen-
dent and is controlled by the common Interval Timer
Frequency Select Register (ITFSR). Buffer registers store
the respective frequency select codes and ensure com-
plete programming independence of each interrupt
channel.
Interrupt masking and programming of the interrupt
priority levels is performed with the aid of the Interval
Timer Interrupt Priority Register (ITIPR).
2.6.1
Interval Timer Registers
The Interval Timer Frequency Select Register (ITFSR) is
I/O mapped to the primary address register of the pre-
scaler/ interval timer address (’F’hex) and the Interval
Timer Interrupt Priority Register (ITIPR) to the corre-
sponding auxiliary register.
The interrupt masks MIA and MIB enable interrupt mask-
ing of INTA and INTB respectively. Each interrupt source
can be programmed with PRA and PRB to one of two
interrupt priority levels. Disabling both interrupts resets
the interval timer and it’s divider chain.
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