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參數(shù)資料
| 型號： | M44C588 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 549K |
| 代理商： | M44C588 |
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M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
29 (44)
2.8
Timer/ Counter Registers
All timer/ counter registers are indirectly addressed using extended addressing as described in section ‘Addresing Per-
pherals‘. An overview of all register and subport addresses is shown in table 6. The Timer/ Counter auxiliary
register (TCX) holds the subport address of the particular register to be accessed.
Timer 0 Interrupt Status Register (T0SR)
Subport address (read access): ’0’hex
Bit 3
Bit 2
Bit 1
Bit 0
T0SR
T0EOM
T0OFL
T0CMP2
T0CMP1
Reset value: 0000b
Note: The Timer 0 status register is reset automatically when read and also when Timer 0 is reset.
T0CMP1, T0CMP2 – Timer 0 compare 1/ compare 2 interrupt status flag
T0OFL
– Timer 0 overflow status flag
T0EOM
– Timer 0 end of measurement status flag
Table 15.
Timer 0 interrupt status register (T0SR)
Code
3 2 1 0
Function
0 0 0 0
No interrupt
x x x 1
Timer 0 compare 1 interrupt event (Timer 0 = T0CP1)
x x 1 x
Timer 0 compare 2 interrupt event (Timer 0 = T0CP2) or external interrupt on BP40
x 1 x x
Timer 0 overflow/ underflow interrupt or external interrupt on BP41
1 x x x
Timer 0 measurement completed
Timer 1 Interrupt Status Register (T1SR)
Subport address (read access): ’1’hex
Bit 3
Bit 2
Bit 1
Bit 0
T1SR
T1EOM
T1OFL
T1CMP2
T1CMP1
Reset value: 0000b
Note: The Timer 1 status register is reset automatically when read and also when Timer 1 is reset.
T1CMP1, T1CMP2 – Timer 1 compare 1/ compare 2 interrupt status flag
T1OFL
– Timer 1 overflow status flag
T1EOM
– Timer 1 end of measurement status flag
Table 16.
Timer 0 interrupt status register (T0SR)
Code
3 2 1 0
Function
0 0 0 0
No interrupt
x x x 1
Timer 1 compare 1 interrupt event (Timer 1 = T1CP1)
x x 1 x
Timer 1 compare 2 interrupt event (Timer 1 = T1CP2) or external interrupt on BP42
x 1 x x
Timer 1 overflow/ underflow interrupt or external interrupt on BP43
1 x x x
Timer 1 measurement completed
For both interrupt status registers (T0SR and T1SR) the interrupt flag will be set whenever the assiciated condition
occurs irrespective of whether the corresponding interrupt is triggered. So, when the interrupt is masked the status flags
will still be set if the interrupt condition occurs. To see exactly when the flags are set, see T0MO and T1MO control
tables.
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