參數(shù)資料
型號(hào)： M44C588
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER
文件頁(yè)數(shù)： 29/44頁(yè)
文件大小： 549K
代理商： M44C588
M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
35 (44)
3
Liquid Crystal Display Driver
This chapter describes the function and the programming
of the integrated LCD driver. It also includes
D Information about the relationship between a typical
7 segment display, the segment and backplane outputs
(for 3:1 and 4:1 multiplex drive modes)
D Waveform examples for the different LCD drive
modes
Figure 26 is a functional block diagram of the LCD driver
circuitry. The internal I/O bus is connected to the LCD
control register (Port 2 auxiliary register) and the LCD
data register (Port 2).
The LCD driver circuitry offers the following features:
D Drives up to 128 display segments
D Supports 3 V or 5 V LCD panels over the full supply
voltage range
D Built-in LCD voltage generation with temperature
compensation (constant LCD contrast)
D Current consumption of LCD panel adaptable to dis-
play size
D Display continues when mC in SLEEP mode
D Programmable multiplex rate (1/3 or 1/4 duty)
D 16 segment drivers configurable by software as
bidirectional ports (2-bit wise)
3.1
Display Data Register
The LCD data register receives the data from the
mC and
writes the data in the shadow register addressed by the
address pointer. After any write access the pointer is
decremented and the next data can be written in the next
data register.
The data in the display buffer is displayed at the LCD. A
logical 1 in the display buffer’s bit-map indicates the ON
state of the corresponding LCD segment. Similiarly a
logical 0 indicates the OFF state. There is a 1:1 correspon-
dence between each stage of the buffer register and the
segment outputs, and between the individual bits of a
buffer nibble and the backplane outputs. The LSB of each
nibble corresponds to the 32 segments operated with
respect of backplane COM0. In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display buffer are time multiplexed
with COM1, COM2 and COM3 respectively. The LCD
specific segment decoding is done via qFORTH software
routines, thus omitting the need for separate decoding
circuitry.
S31
S30
S29
S03
S02
S01
S00
LCD drivers
COM3
COM2
COM1
COM0
Prescaler
Voltage
timing
generator
and
LCD
Control register
LCD
Data port
Address
pointer
LCD
Port
configuration
register
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
SR31 SR30 SR29
SR3 SR2 SR1 SR0
LCD display buffer
Shadow register
Display rotate
Power
save
Mux rate
SUBCL
I/O bus
Display
blanking
Set address pointer
Frame frequency
14013
Figure 26. LCD driver – functional block diagram
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