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參數(shù)資料
| 型號： | M44C588 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| 文件頁數(shù)： | 4/44頁 |
| 文件大?。?/td> | 549K |
| 代理商： | M44C588 |
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M44C588
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
Preliminary Information
12 (44)
these oscillator types or an external input clock can be
selected to generate the system clock (SYSCL).
In applications that do not require exact timing, it is
possible to use the fully integrated RC-oscillator 1
without any external components. The RC-oscillator 2 is
more precise whereby the oscillator frequency can be
trimmed with an external resistor attached between
SCLIN and VDD. In this configuration, the RC-
oscillator 2 frequency can be maintained stable to within
a tolerance of
± 10% over the full operating temperature
and voltage range.
The clock module is programmable via software with the
clock manage register (CM) and the system configuration
register (SC). The required oscillator configuration has to
be selected with the OS1[1:0]-bits in the SC-register. A
programmable 4-bit divider stage allows the adjustment
of the system clock speed. A special feature of the clock
management is that an external oscillator may be used and
switched on and off via a port pin for the power-down
mode. Before the external clock is switched off, the
internal RC-oscillator 1 must be selected with the CCS-
bit and then the SLEEP mode may be activated. In this
state an interrupt can wake up the controller with the RC-
oscillator, and the external oscillator can be activated and
selected by software. A synchronization stage avoids too
short clock periods if the clock source or the clock speed
is changed.
Ext. clock
ExIn
ExOut
Stop
RC oscillator2
RCOut2
Stop
R
Trim
4–MHz oscillator
4Out
Stop
Oscin
Oscout
32–kHz oscillator
32Out
Oscin
Oscout
RC
oscillator 1
RCOut1
Control
Stop
IN1
IN2
/2
Divider chain
Sleep
Stop
NSTOP
CCS
CSS1
CSS0
CM:
OS1
OS0
SUBCL
SYSCL
SC:
*
OSCIN
*
OSCOUT
*
mask option
32 kHz
13386
SCLIN
SYSCLmax
/8
SYSCLmax/64
RC[1:0]
SC:
to CPU
and
Timer/
counter
Figure 10. Clock module
Table 4. Clock modes
Mode
Clock Source for SYSCL
Clock Source for SUBCL
OS1
OS0
CCS = 1
CCS = 0
CCS = 1
CCS = 0
1
1
1
RC-oscillator 1 (intern)
External input clock
SYSCL max/64
SCLIN / 128
2
0
1
RC-oscillator 1 (intern)
RC-oscillator 2 with
external trimming resistor
SYSCL max/64
SYSCL max/64
3
1
0
RC-oscillator 1 (intern)
4-MHz oscillator
SYSCL max/64
fxtal / 128
4
0
0
RC-oscillator 1 (intern)
32-kHz oscillator
32 kHz
The clock module generates two output clocks. One is the
system clock (SYSCL) and the other the periphery clock
(SUBCL). The SYSCL can supply the core and the
peripherals and the SUBCL can supply only the
peripherals with clocks. The modes for clock sources are
programmable with the OS1-bit and OS0-bit in the SC-
register and the CCS-bit in the CM-register.
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