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參數(shù)資料
| 型號： | M44C588 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 549K |
| 代理商： | M44C588 |
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M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
21 (44)
2.3
Bidirectional Port B
Master reset
Q
V
DD
V
DD
BPBy
Mask options
*
PBDATy
PBDDRy
I/O Bus
D
I/O Bus
*
Pull-up
Pull-down
V
DD
*
Static
pull-up
(Data out)
(Direction)
*
S
D
*
S
*
V
DD
Static
pull-down
14010
Figure 19. Bidirectional Port B
Port B includes a bitwise programmable Data Direction
Register (PBDDR), which allows the individual program-
ming of each port bit as input or output. It also opens up
the possibility of reading the pin condition when in output
mode. This is a useful feature for self testing and for data
bus applications.
2.3.1
Port Monitor Module
In addition to the standard I/O functions, Port B (BPB3 –
BPB0) is equipped with port monitor module. This mod-
ule is connected across all four port pins (see figure 20)
and generates an interrupt should a preprogrammed tran-
sition occur on any of the pins. This allows interrupt
driven port scanning without the power consuming task
of continuously polling the port inputs.
Using the Port Interrupt Control Register (PBICR), each
pin can be selected individually. A non-selected pin can-
not generate an interrupt. The Port Interrupt Priority
Register (PBIPR) allows masking of each interrupt, defi-
nition of the interrupt generating signal transition and
programming of the interrupt priority level.
The Port Interrupt Priority Registers PBIPR is I/O
mapped to the primary address registers of the Port Moni-
tor Module addresse ’A’h. The Port Interrupt Control
Registers PBICR is mapped to the corresponding auxil-
iary register.
PBICR
BPB3
BPB2
BPB1
BPB0
Decoder
Connected to Port B
INT5
INT7
INT3
INT1
INT5
INT7
INT3
INT1
PBIPR
ENB3
ENB2
ENB1
ENB0
IMB
ITRB
PRB1
PRB2
00
01
10
11
PRB1 PRB2
96 115
Figure 20. Port B monitor input module
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