參數(shù)資料
型號(hào)： M44C588
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER
文件頁(yè)數(shù)： 6/44頁(yè)
文件大?。?/td> 549K
代理商： M44C588
M44C588
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
Preliminary Information
14 (44)
32–kHz
oscillator
32Out
13380
OSCIN
OSCOUT
*
Oscin
C1
*
C2
Oscout
XTAL
32 kHz
*
mask option
Figure 15. 32-kHz crystal oscillator
1.5.3
Clock Management Register (CM)
The clock management register (CM) controls the system clock divider chain, as well as the peripheral clock in the
power-down modes.
Auxiliary register address: ’E’hex
Bit 3
Bit 2
Bit 1
Bit 0
CM:
NSTOP
CCS
CSS1
CSS0
Reset value: 1111b
NSTOP
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock (SUBCL) during the core is in SLEEP mode, with the
exception of the 32-kHz crystal oscillator SUBCL clock.
NSTOP = 1, enables the peripheral clock (SUBCL) during the core in SLEEP mode
CCS
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
RC-oscillator 2 (with the external resistor) will generate SYSCL dependent on the setting of
OS0 and OS1 in the system configuration register
CSS[1:0]
Core Speed Select
These two bits control the system clock divider chain
Auxiliary register address: ’E’hex
CSS1
CSS0
Divider
Note
0
0
16
SYSCLmax/8
0
1
8
SYSCLmax/4
1
0
4
SYSCLmax/2
1
1
2
Reset value = SYSCLmax
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