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參數(shù)資料
| 型號： | M44C588 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| 文件頁數(shù)： | 2/44頁 |
| 文件大小： | 549K |
| 代理商： | M44C588 |
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M44C588
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
Preliminary Information
10 (44)
Table 2. Interrupt priority table
Interrupt
Priority
ROM Address
Maskable
Interrupt Opcode
INT0
lowest
040h
Yes
C8h (SCALL 040h)
INT1
|
080h
Yes
D0h (SCALL 080h)
INT2
|
0C0h
Yes
D8h (SCALL 0C0h)
INT3
|
100h
Yes
E8h (SCALL 100h)
INT4
|
140h
Yes
E8h (SCALL 140h)
INT5
|
180h
Yes
F0h (SCALL 180h)
INT6
↓
1C0h
Yes
F8h (SCALL 1C0h)
INT7
highest
1E0h
Yes
FCh (SCALL 1E0h)
1.3.1
Hardware Interrupts
Table 3. Hardware interrupts
Interrupt
Possible Interrupt Priorities
RST
Interrupt Mask
Function
Source
0
1
2
3
4
5
6
7
Register
Bit
NRST external
X
–
–
low level active
Watchdog
#
–
–
1/2 – 2 sec. time out
Port B coded reset
#
–
–
level any inputs
Port B monitor
*
*
*
*
PBIPR
3
any edge, any input
Port 6 external INTX
*
*
*
*
–
0
any edge, any input
Port 6 external INTY
*
*
*
*
–
0
any edge, any input
Serial I/O
*
*
*
*
SIM0
0
SSI receive buffer full,
transmit buffer empty
Interval timer INTA
*
*
ITIPR
0
1 of 8 frequencies
(1 – 128Hz)
Interval timer INTB
*
*
ITIPR
1
1 of 8 frequencies
(8 – 8192Hz)
Timer 0
*
*
*
*
T0CR
0
overflow/compare/
end measurement
Timer 1
*
*
*
*
T1CR
0
overflow/compare/
end measurement
X = hardwired (neither optional or software configurable)
# = customer mask option (see “Ordering Information”)
* = software configurable (see “Peripheral Modules” section for further details)
In the M44C588 there are eleven hardware interrupt
sources which can be programmed to occupy a variety of
priority levels. Each source can be individually masked
by mask bits in the corresponding control registers. An
overview of the possible hardware configurations is
shown in table 3.
1.3.2
Software Interrupts
The programmer can generate interrupts using the soft-
ware interrupt instruction (SWI) which is supported in
qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
hardware triggered interrupt.
The SWI instruction takes the top two elements from the
expression stack and writes the corresponding bits via the
I/O bus to the interrupt pending register. Thus using the
SWI instruction, interrupts can be re-prioritised or lower
priority processes scheduled for later execution.
1.4
Master Reset
The master reset forces the CPU into a well-defined
condition, is unmaskable and is activated independent of
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