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參數(shù)資料
| 型號： | M44C588 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 549K |
| 代理商： | M44C588 |
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M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
23 (44)
2.4
Bidirectional Port 6
This 4-bit bidirectional port can be used as bitwise pro-
grammable I/O. The port pins can also be used as external
interrupt inputs (see figures 21 and 22). Both interrupts
can be masked or independently configured to trigger on
either edge. The interrupt priority levels are also pro-
grammable. The interrupt configuration is controlled by
the Port 6 Interrupt Priority Register (P6IPR), the Exter-
nal Interrupt X Source Select Register (IRXCR) and the
External Interrupt Y Source Register (IRYCR). The port
direction is controlled by the Port 6 Data Direction Regis-
ter (P6DDR) An additional low resistance pull-up
transistor provides an internal static pull-up for serial bus
applications (mask option).
In output mode (P6DDR bit = 0), the respective Port Data
Register (P6DAT) bit will appear on the port pin, driven
by an output port driver stage which can be mask pro-
grammed as open drain, or full complementary CMOS.
With an IN instruction the actual pin state can be read
back at any time into the controller without changing the
port directional mode. So, for example should the output
port be mask configured as an open drain driver, as long
as the output transistor is off, the controller is able to re-
ceive external data on this pin without switching into
input mode.
In input mode (P6DDR bit = 1), the output driver stage is
deactivated, so that an IN instruction will directly read the
pin state which can be driven from an external source. In
this case the state of the Port Data Register (P6DAT),
although not appearing at the pin itself remains
unchanged. High resistance mask selectable pull-up or
pull-down transistors are automatically switched onto the
port pin in input mode. The Port Data Register is written
with an OUT instruction to the respective port address.
The Port 6 Data Register (P6DAT) is I/O mapped to the
primary address register of address ’6’hex and the Port 6
Control Register (P6CR) to the corresponding auxiliary
register. The Interrupt Priority Register (P6IPR) and the
External Interrupt X/Y Priority Registers IRXCR and
IRYCR) are indirectly addressed by using extended ad-
dressing mode as descibed in section ”Addressing
Peripherals” and I/O mapped to the Port 7 subport register
addresses ’5’hex, ’6’hex and ’7’hex (see table 6).
Master reset
Q
V
DD
V
DD
BP6y
Mask options
*
P6DATy
I/O Bus
D
IN enable
I/O Bus
*
Pull-up
Pull-down
V
DD
*
Static
pull-up
(Data out)
*
S
14011
*
V
DD
Static
pull-down
Figure 21. Bidirectional Port 6
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