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參數(shù)資料
| 型號： | M44C588 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 549K |
| 代理商： | M44C588 |
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M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
9 (44)
7
6
5
4
3
2
1
0
Priority
level
INT5 active
INT7 active
INT2 pending
SWI0
INT2 active
INT0 pending
INT0 active
INT2
RTI
INT5
INT3 active
INT3
RTI
INT7
Time
Main / Autosleep
Main /Autosleep
94 8978
Figure 8. Interrupt handling
Interrupt Processing
For processing the eight interrupt levels the MARC4 in-
cludes an interrupt controller with two 8-bit wide
“interrupt pending” and “interrupt active” registers. The
interrupt controller samples all interrupt requests during
every non-I/O instruction cycle and latches these in the
interrupt pending register. If no higher priority interrupt
is present in the interrupt active register it signals the CPU
to interrupt the current program execution. If the interrupt
enable bit is set the processor enters an interrupt acknowl-
edge cycle. During this cycle a short call (SCALL)
instruction to the service routine is executed and the cur-
rent PC is saved on the return stack. An interrupt service
routine is finished with the RTI instruction. This instruc-
tion
sets
the
interrupt
enable
flag,
resets
the
corresponding bits in the interrupt pending/active register
and fetches the return address from the return stack to the
program counter. When the interrupt enable flag is reset
(triggering of interrupt routines are disabled), the execu-
tion of new interrupt service routines is inhibited but not
the logging of the interrupt requests in the interrupt pend-
ing register. The execution of the interrupt will be delayed
until the interrupt enable flag is set again. Note that inter-
rupts are only lost if an interrupt request occurs while the
corresponding bit in the pending register is still set (i.e.
the interrupt service routine is not yet finished).
It should also be realised that automatic stacking of the
RBR is not carried out by the hardware and so if ROM
banking is used, the RBR must be stacked on the expres-
sion stack by the application program and restored before
the RTI. After a master reset (power-on, external or
watchdog reset), the interrupt enable flag and the inter-
rupt pending and interrupt active register are all reset.
Interrupt Latency
The interrupt latency is the time from the occurrence of
the interrupt to the interrupt service routine being acti-
vated. In the MARC4 this is extremely short taking
between 3 to 5 machine cycles depending on the state of
the core.
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