M44C588

Rev. A1, 11-Nov-97

Preliminary Information

28 (44)

Primary register address (write only): ’F’hex

Bit 3

Bit 2

Bit 1

Bit 0

FS3 ... 0 – Frequency select code

Table 14.Interval Timer Frequency Select Register (ITFSR)

Code

3 2 1 0

Function

SUBCL

divide by

SUBCL

= 32 kHz

Code

3 2 1 0

Function

SUBCL

divide by

SUBCL

= 32 kHz

0 0 0 0

INTA

Select 1 Hz

1 0 0 0

INTB

Select 8 Hz

Select 2 Hz

1 0 0 1

Select 16 Hz

Select 4 Hz

1 0 1 0

Select 64 Hz

0 0 1 1

Select 8 Hz

1 0 1 1

Select 256 Hz

0 1 0 0

Select 16 Hz

1 1 0 0

Select 1024 Hz

0 1 0 1

Select 32 Hz

1 1 0 1

Select 2048 Hz

0 1 1 0

Select 64 Hz

1 1 1 0

Select 4096 Hz

0 1 1 1

Select 128 Hz

1 1 1 1

Select 8192 Hz

The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2–FS0).

This allows independent programming of interval times for INTA and INTB.

17-stage binary counter

SUBCL

CK

R

RR

R

RR

R

RR

R

Read

WDRES

V

*

Watchdog enable

*

2

NRST

Master

Reset

DD

14

2

15

2

16