參數(shù)資料
型號(hào)： M44C588
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 4 MHz, MICROCONTROLLER
文件頁(yè)數(shù)： 25/44頁(yè)
文件大?。?/td> 549K
代理商： M44C588
M44C588
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 11-Nov-97
31 (44)
Timer 1 Compare Register 2 (T0CP2)
Subport address (write access): ’B’hex
Bit 3
Bit 2
Bit 1
Bit 0
T1CP2
First write cycle
T1CP23
T1CP22
T1CP21
T1CP20
Reset value: xxxxb
Bit 7
Bit 6
Bit 5
Bit 4
Second write cycle
T1CP27
T1CP26
T1CP25
T1CP24
Reset value: xxxxb
T1CP23 ... T1CP20 – Timer 1 compare register 2 data (low nibble) – first write cycle
T1CP27 ... T1CP24 – Timer 1 compare register 2 data (high nibble) – second write cycle
Timer/ Counter Compare Register (T1CP2)
Subport address: ‘B‘hex
Timer/ counter subport pointer (TCX) address: ‘9‘hex
The compare registers (T0CP1, T0CP2, T1CP1 and T1CP2) are all 8-bit wide and must accessed as byte wide subports
(see section ‘Addressing Peripherals‘). They are writen low nibble first followed by the high nibble. Any time interrupts
are suppressed automatically until the complete compare value has been transferred.
Timer 0 Capture Register (T0CA)
Subport address (read access): ’8’hex
Bit 3
Bit 2
Bit 1
Bit 0
T0CA
Second read cycle
T0CA3
T0CA2
T0CA1
T0CA0
Reset value: 0000b
Bit 7
Bit 6
Bit 5
Bit 4
First read cycle
T0CA7
T0CA6
T0CA5
T0CA4
Reset value: 0000b
T0CA7. .. T0CA4 – Timer 0 capture register data (high nibble) – first read cycle
T0CA3 ... T0CA0 – Timer 0 capture register data (low nibble) – second read cycle
Timer/ Counter Compare Register (T0CP1)
Subport address: ‘8‘hex
Timer/ counter subport pointer (TCX) address: ‘9‘hex
Timer 1 Capture Register (T1CA)
Subport address (indirect read access): ’9’hex
Bit 3
Bit 2
Bit 1
Bit 0
T1CA
Second read cycle
T1CA3
T1CA2
T1CA1
T1CA0
Reset value: 0000b
Bit 7
Bit 6
Bit 5
Bit 4
First read cycle
T1CA7
T1CA6
T1CA5
T1CA4
Reset value: 0000b
T1CA7 ... T1CA4 – Timer 1 Capture Register Data (high nibble) – first read cycle
T1CA3 ... T1CA0 – Timer 1 Capture Register Data (low nibble) – second read cycle
Timer/ Counter Compare Register (T0CP1)
Subport address: ‘9‘hex
Timer/ counter subport pointer (TCX) address: ‘9‘hex
The 8-bit capture registers (T0CA and T1CA) are read as byte wide subports. Note, however, unlike the writing to the
compare registers, the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading
the first nibble and held until the complete byte has been read. During this transfer the timer is free to continue counting.
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