
Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 89 of 124
4571 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB3
(Transfer data to Accumulator and register B from timer 3)
Instruc-
tion
code
1
0
0
1
1
1
0
0
D
9
D
0
0 2
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
7
2 16
1
1
-
-
Opera-
tion:
(B)
←
(T3
7
T3
4
)
(A)
←
(T3
3
T3
0
)
Grouping:
Description: Transfers the high-order 4 bits (T3
7
T3
4
) of timer 3 to reg-
ister B.
Transfers the low-order 4 bits (T3
3
T3
0
) of timer 3 to regis-
ter A.
Timer operation
TABE
(Transfer data to Accumulator and register B from register E)
Instruc-
tion
code
0
0
0
0
1
0
1
0
D
9
D
0
0 2
Number of
words
Number of
cycles
Flag CY
Skip condition
1
0
2
A 16
1
1
-
-
Opera-
tion:
(B)
←
(E
7
E
4
)
(A)
←
(E
3
E
0
)
Grouping:
Description: Transfers the high-order 4 bits (E
7
E
4
) of register E to reg-
ister B, and low-order 4 bits of register E to register A.
Register to register transfer
TABP p
(Transfer data to Accumulator and register B from Program memory in page p)
Instruc-
tion
code
0
0
1
0 p
5
p
4
p
3
p
2
p
1
p
0
2
D
9
D
0
Number of
words
Number of
cycles
Flag CY
Skip condition
0
8
+p
p16
1
3
-
-
Opera-
tion:
(SP)
←
(SP) + 1
(SK(SP))
←
(PC)
(PC
H
)
←
p
(PC
L
)
←
(DR
2
DR
0
, A
3
A
0
)
(B)
←
(ROM(PC))
7
4
(A)
←
(ROM(PC))
3
0
(UPTF)
←
1
(DR
1
, DR
0
)
←
(ROM(PC))
9
,
8
(DR
2
)
←
0
(PC)
←
(SK(SP))
(SP)
←
(SP)
1
Grouping:
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to
0 are the ROM pattern in address (DR
2
DR
1
DR
0
A
3
A
2
A
1
A
0
)
2
specified by
registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-
order 2 bits (DR
1
, DR
0
) of register D, and “0” is stored to the least significant
bit (DR
2
) of register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
M34571G4 : p = 0 to 31
M34571G6 : p = 0 to 47
M34571GD : p = 0 to 127
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
Arithmetic operation
TABPS
(Transfer data to Accumulator and register B from Prescaler)
Instruc-
tion
code
1
0
0
1
1
1
0
1
D
9
D
0
1 2
Number of
words
Number of
cycles
Flag CY
Skip condition
0
2
7
5 16
1
1
-
-
Opera-
tion:
(B)
←
(TPS
7
TPS
4
)
(A)
←
(TPS
3
TPS
0
)
Grouping:
Description: Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
Timer operation