Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 4 of 124
4571 Group
PERFORMANCE OVERVIEW
Table 2
Performance overview
Parameter
Function
Number of basic instructions
M34571G4/G6
M34571GD
126
128
0.5
μ
s (Oscillation frequency 6 MHz: through mode)
4096 words
×
10 bits
6144 words
×
10 bits
16384 words
×
10 bits
128 words
×
4 bits
Five independent I/O ports;
The output structure of ports D
0–
D
3
is switched by software.
Port D
4
is also used as CNTR0, respectively.
4-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software.
4-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software.
2-bit I/O port; a pull-up function and a key-on wakeup function can be switched by software.
Ports P2
0
and P2
1
are also used as INT0 and INT1, respectively.
2-bit I/O port ; the output structure is switched by software.
1-bit output port (CMOS output only); port C is also used as CNTR1 pin.
1-bit input port ; a key-on wakeup function can be switched by software.
1-bit I/O port ; CNTR0 pin is also used as port D
4
.
1-bit output port ; CNTR1 pin is also used as port C.
1-bit input port ; INT0 and INT1 are also used as ports P2
0
and P2
1
, respectively.
8-bit timer with a reload register and carrier wave output auto-control function, and has
an event counter.
8-bit timer with a reload register.
8-bit timer with two reload registers and carrier wave generation function.
16-bit timer, fixed dividing frequency (timer for monitor)
Built-in
Typ. 1.65 V (Ta=25 °C)
Typ. 1.75 V (Ta=25 °C)
Typ. 1.85 V (Ta=25 °C)
6 sources (two for external, three for timers, voltage drop detection circuit)
1 level
8 levels
CMOS sillicon gate
24-pin plastic molded SSOP (PRSP0024GA-A)
-20 to 85 °C
1.8 to 5.5 V (It depends on oscillation frequency and operation mode)
0.3 mA (Ta = 25 °C, V
DD
= 3.0 V, f(X
IN
)=4 MHz, f(STCK)=f(X
IN
)/8)
0.1
μ
A (Ta = 25 °C, output transistor is cut-off state)
Minimum instruction execution time
Memory sizes
ROM
M34571G4
M34571G6
M34571GD
RAM
D
0–
D
4
I/O port
I/O (Input is
examined by
skip decision)
I/O
I/O
I/O
P0
0
P0
3
P1
0
P1
3
P2
0
, P2
1
P3
0
, P3
1
C
K
CNTR0
CNTR1
INT0, INT1
Interrupt input
Timer 1
I/O
Output
Input
Timer I/O
Timer output
Timer
Timer 2
Timer 3
Watchdog timer
Power-on reset circuit
Voltage drop
detection circuit
Reset occurrence
Reset release
Interrupt occurrence
Source
Nesting
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Power source voltage
Power
dissipation
(Typ. value)
At active mode
At RAM back-up