
Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 6 of 124
4571 Group
PORT FUNCTION
DEFINITION OF CLOCK AND CYCLE
Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
Clock (f(X
IN
)) by the external ceramic resonator
Clock (f(X
IN
)) by the external input
System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the register MR.
Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.
Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
Note 1.The frequency divided by 8 is selected after system is
released from reset.
Table 5
Port function
Port
Pin
Input
Output
I/O
(5)
Output
structure
N-channel
open-drain/
CMOS
N-channel
open-drain
I/O unit
Control
instructions
SD, RD
SZD, CLD
Control
registers
FR1
Remark
Port D
D
0
D
3
1 bit
Programmable output
structure selection function
D
4
/CNTR0
W1
W2
W5
PU0
K0
Port P0
P0
0
P0
1
P0
2
P0
3
P1
0
P1
1
P1
2
P1
3
P2
0
/INT0
P2
1
/INT1
P3
0
P3
1
I/O
(4)
N-channel
open-drain
4 bits
OP0A
IAP0
Programmable pull-up and
key-on wakeup function
Port P1
I/O
(4)
N-channel
open-drain
4 bits
OP1A
IAP1
PU1
K1
Programmable pull-up and
key-on wakeup function
Port P2
I/O
(2)
I/O
(2)
N-channel
open-drain
N-channel
open-drain/
CMOS
CMOS
2 bits
OP2A
IAP2
OP3A
IAP3
PU2
K2, I1, I2, L1
FR0
Programmable pull-up and
key-on wakeup function
Programmable output
structure selection function
Port P3
2 bits
Port C
C/CNTR1
Output
(1)
Input
(1)
1 bit
RCP
SCP
IAK
W1, W3, W5
Port K
K
-
1 bit
K2
Programmable key-on
wakeup function
Table 6
Table Selection of system clock
Register MR
MR
3
1
1
0
0
System clock
Operation mode
MR
2
1
0
1
0
f(STCK) = f(X
IN
)/8
f(STCK) = f(X
IN
)/4
f(STCK) = f(X
IN
)/2
f(STCK) = f(X
IN
)
Frequency divided by 8 mode
Frequency divided by 4 mode
Frequency divided by 2 mode
Frequency through mode