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參數資料
| 型號： | M34571G4 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片4位微機的CMOS |
| 文件頁數： | 18/126頁 |
| 文件大?。?/td> | 1627K |
| 代理商： | M34571G4 |
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Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 18 of 124
4571 Group
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 20).
Program counter (PC)
An interrupt address is set in program counter. The address to
be executed when returning to the main routine is
automatically stored in the stack register (SK).
Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
Interrupt request flag
Only the request flag for the current interrupt source is cleared
to “0” (the voltage drop detection circuit interrupt request flag
is excluded)
Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is
executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an
interrupt address. Use the RTI instruction to return from an
interrupt service routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed just
before the RTI instruction, interrupts are enabled after returning
the main routine. (Refer to Figure 19)
Fig 19. Program example of interrupt processing
Fig 20. Internal state when interrupt occurs
Fig 21. Interrupt system diagram
Main
routine
Interrupt
occurs
Interrupt is
enabled
Interrupt
service routine
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
Each interrupt address
Program counter (PC)
The address of main routine to be
executed when returning
Stack register (SK)
0 (Interrupt disabled)
Interrupt enable flag (INTE)
0 (excluding voltage drop detection interrupt request flag)
Interrupt request flag (only the flag for the current interrupt
source)
Stored in the interrupt stack register (SDP)
automatically
Data pointer, carry flag, registers A and B, skip flag
EXF0
Request flag
(state retained)
V1
0
Enable bit
Enable flag
Address 0
INT0 pin interrupt
waveform input
uTimer 2
T1F
V1
2
Address 4
in page 1
uTimer 1
T2F
V1
3
Address 6
T3F
V2
0
Address 8
in page 1
Activated
condition
INTE
uTimer 3
EXF1
V1
1
Address 2
INT1 pin interrupt
waveform input
VDF
V2
3
Address E
in page 1
when supply voltage
goes lower than
specified value
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M34571G4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G6 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G6FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G6-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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