參數(shù)資料
型號(hào): M34571G4
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機(jī)的CMOS
文件頁(yè)數(shù): 67/126頁(yè)
文件大?。?/td> 1627K
代理商: M34571G4
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Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 67 of 124
4571 Group
INSTRUCTIONS
Each instruction is described as follows;
1.Index list of instruction function
2.Machine instructions (index by alphabet)
3.Machine instructions (index by function)
4.Instruction code table
SYMBOL
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Note 1.The 4571 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased
by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if
the TABP p, RT, or RTS instruction is skipped.
Symbol
Contents
Symbol
T1F
T2F
T3F
WDF1
WEF
INTE
EXF0
EXF1
VDF
P
D
P0
P1
P2
P3
Contents
A
B
DR
E
V1
V2
I1
I2
PA
W1
W2
W3
W5
MR
K0
K1
K2
L1
PU0
PU1
PU2
FR0
FR1
X
Y
Z
DP
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Interrupt control register I2 (4 bits)
Timer control register PA (2 bits)
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W5 (4 bits)
Clock control register MR (4 bits)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Key-on wakeup control register L1 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Pull-up control register PU2 (4 bits)
Port output structure control register FR0 (4 bits)
Port output structure control register FR1 (4 bits)
Register X (4 bits)
Register Y (4 bits)
Register Z (2 bits)
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
External 1 interrupt request flag
Voltage drop detection circuit interrupt request flag
Power down flag
Port D (5 bits)
Port P0 (4 bits)
Port P1 (4 bits)
Port P2 (2 bits)
Port P3 (2 bits)
x
y
z
p
n
i
j
A
3
A
2
A
1
A
0
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
Binary notation of hexadecimal variable A
(same for others)
( )
M (DP)
a
p, a
Direction of data movement
Contents of registers and memories
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a
6
a
5
a
4
a
3
a
2
a
1
a
0
Label indicating address a
6
a
5
a
4
a
3
a
2
a
1
a
0
in page
p
6
p
5
p
4
p
3
p
2
p
1
p
0
PC
PC
H
PC
L
SK
SP
CY
RPS
R1L
R2
R3L
R3H
PS
T1
T2
T3
Program counter (14 bits)
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits
×
8)
Stack pointer (3 bits)
Carry flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
Timer 3 reload register (8 bits)
Timer 3 reload register (8 bits)
Prescaler
Timer 1
Timer 2
Timer 3
C
+
x
Hex. C + Hex. number x (also same for others)
Decision of state shown before “”
Data exchange between a register and memory
AND
OR
Logical multiplication
Logical addition
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