參數(shù)資料
型號: M34571G4
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
中文描述: 單芯片4位微機的CMOS
文件頁數(shù): 21/126頁
文件大小: 1627K
代理商: M34571G4
Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 21 of 124
4571 Group
EXTERNAL INTERRUPTS
The 4571 Group has the external 0 interrupt and external 1
interrupt. An external interrupt request occurs when a valid
waveform is input to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
Fig 23. External interrupt circuit structure
Table 14 External interrupt activated conditions
Name
Input pin
Activated condition
Valid waveform
selection bit
I1
1
I1
2
External 0 interrupt
P2
0
/INT0
When the next waveform is input to P2
0
/INT0 pin
Falling waveform (
H
L
)
Rising waveform (
L
H
)
Both rising and falling waveforms
When the next waveform is input to P2
1
/INT1 pin
Falling waveform (
H
L
)
Rising waveform (
L
H
)
Both rising and falling waveforms
External 1 interrupt
P2
1
/INT1
I2
1
I2
2
Key-on wakeup input
SNZI0 instruction
(Note 1)
L1
1
0
1
Edge detection circuit
Level detection circuit
P2
0
/INT0
I1
3
I1
2
Falling
0
1
Rising
L1
0
I1
1
0
1
One-sided edge
detection circuit
Both edges
detection circuit
Skip
EXF0
External 0
interrupt
Timer 1 count start
synchronization
circuit input
(Note 2)
(Note 3)
Note 1: This symbol represents a parasitic diode on the port.
2: When
IX
2
= 0(X=0 or 1)
is 0, “L” level is detected.
When IX
2
is 1, “H” level is detected.
3: When IX
2
is 0, falling edge is detected.
When IX
2
is 1, rising edge is detected.
(Note 1)
Key-on wakeup input
SNZI1 instruction
(Note 1)
L1
3
0
1
Edge detection circuit
Level detection circuit
P2
1
/INT1
I2
3
I2
2
Falling
0
1
Rising
L1
2
I2
1
0
1
One-sided edge
detection circuit
Both edges
detection circuit
Skip
EXF1
External 1
interrupt
(Note 2)
(Note 3)
(Note 1)
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