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參數(shù)資料
| 型號(hào)： | M34571G4 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片4位微機(jī)的CMOS |
| 文件頁數(shù)： | 63/126頁 |
| 文件大?。?/td> | 1627K |
| 代理商： | M34571G4 |
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Rev.1.02
REJ03B0179-0102
May 25, 2007
Page 63 of 124
4571 Group
CONTROL REGISTERS
Note 1.”R” represents read enabled, and “W” represents write enabled.
Note 2.When the contents of I1
2
and I1
3
are changed, the external interrupt request flag EXF0 may be set.
Note 3.When the contents of I2
2
and I2
3
are changed, the external interrupt request flag EXF1 may be set.
Interrupt control register V1
at reset : 0000
2
at RAM back-up : 0000
2
R/W
TAV1/TV1A
V1
3
Timer 2 interrupt enable bit
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
V1
2
Timer 1 interrupt enable bit
V1
1
External 1 interrupt enable bit
V1
0
External 0 interrupt enable bit
Interrupt control register V2
at reset : 0000
2
at RAM back-up : 0000
2
R/W
TAV2/TV2A
V2
3
Voltage drop detector interrupt enable bit
0
1
0
1
0
1
0
1
Interrupt disabled (SNZVD instruction is valid)
Interrupt enabled (SNZVD instruction is invalid)
V2
2
Not used
This bit has no function, but read/write is enabled.
V2
1
Not used
This bit has no function, but read/write is enabled.
V2
0
Timer 3 interrupt enable bit
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
Interrupt control register I1
at reset : 0000
2
at RAM back-up : state retained
R/W
TAI1/TI1A
I1
3
INT0 pin input control bit (Note 2)
0
1
INT0 pin input disabled
INT0 pin input enabled
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Timer 1 disabled
Timer 1 enabled
I1
2
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
0
1
I1
1
INT0 pin edge detection circuit control bit
0
1
0
1
I1
0
INT0 pin
timer 1 control enable bit
Interrupt control register I2
at reset : 0000
2
at RAM back-up : state retained
R/W
TAI2/TI2A
I2
3
INT1 pin input control bit (Note 3)
0
1
INT0 pin input disabled
INT0 pin input enabled
Falling waveform (“L” level of INT0 pin is recognized with the SNZI1
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
I2
2
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
0
1
I2
1
INT1 pin edge detection circuit control bit
0
1
0
1
I2
0
Not used
This bit has no function, but read/write is enabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M34571G4FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G4-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G6 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G6FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34571G6-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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