參數(shù)資料
型號: M30L0R8000B0ZAQE
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝: 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88
文件頁數(shù): 41/83頁
文件大小: 1569K
代理商: M30L0R8000B0ZAQE
Obsolete
Product(s)
- Obsolete
Product(s)
M30L0R8000T0, M30L0R8000B0
46/83
Figure 12. Synchronous Burst Read AC Waveforms
AI10591
DQ0-DQ15
E
G
A0-A23
L
WAIT
K
(4)
VALID
ADDRESS
tLLLH
tAVLH
tGLQX
tAVKH
tLLKH
tELKH
tKHAX
tKHQX
tKHQV
NOT
VALID
Note
1
Note
2
Note
2
tKHTX
tEHQX
tEHQZ
tGHQX
tGHQZ
Hi-Z
VALID
Note
2
tELTV
tKHTV
tEHTZ
Address
Latch
X
Latency
Valid
Data
Flow
Boundary
Crossing
Valid
Data
Standby
Note
1.
The
n
umber
of
cloc
k
cycles
to
be
inser
ted
depends
on
the
X
latency
set
in
the
Burst
Configur
ation
Register
.
2.
The
W
AIT
signal
can
be
configured
to
be
activ
e
dur
ing
w
ait
state
or
one
cycle
bef
ore
.W
AIT
signal
is
activ
e
Lo
w
.
3.
Address
latched
and
data
output
on
the
r
ising
cloc
k
edge
.
4.
Either
the
r
ising
or
the
f
alling
edge
of
the
cloc
k
signal,
K,
can
be
configured
as
the
activ
e
edge
.Here
,the
activ
e
edge
of
K
is
the
r
ising
one
.
tEHEL
Hi-Z
tGLTV
相關PDF資料
PDF描述
M30L0T8000B0ZAQE 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
M31002AMLJ1000.000000MHZ VCXO, CLOCK, 1000 MHz, LVDS OUTPUT
M31016AUMJ1000.000000MHZ VCXO, CLOCK, 1000 MHz, CMOS OUTPUT
M31002AGMJ1000.000000MHZ VCXO, CLOCK, 1000 MHz, CMOS OUTPUT
M31002BMMJ1000.000000MHZ VCXO, CLOCK, 1000 MHz, CMOS OUTPUT
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