- 您現(xiàn)在的位置：買賣IC網 > PDF目錄296349 > M30L0R8000B0ZAQE (STMICROELECTRONICS) 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88 PDF資料下載
參數(shù)資料
| 型號： | M30L0R8000B0ZAQE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88 |
| 封裝： | 8 X 10 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-88 |
| 文件頁數(shù)： | 3/83頁 |
| 文件大?。?/td> | 1569K |
| 代理商： | M30L0R8000B0ZAQE |
第1頁第2頁當前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
Obsolete
Product(s)
- Obsolete
Product(s)
11/83
M30L0R8000T0, M30L0R8000B0
SIGNAL DESCRIPTIONS
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A23). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Input/Output (DQ0-DQ15). The Data I/O
output the data stored at the selected address dur-
ing a Bus Read operation or input a command or
the data to be programmed during a Bus Write op-
eration.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
at VILand Reset is at VIH the device is in active
mode. When Chip Enable is at VIH the memory is
deselected, the outputs are high impedance and
the power consumption is reduced to the stand-by
level.
Output Enable (G). The Output Enable input
controls data outputs during the Bus Read opera-
tion of the memory.
Write Enable (W). The Write Enable input con-
trols the Bus Write operation of the memory’s
Command Interface. The data and address inputs
are latched on the rising edge of Chip Enable or
Write Enable whichever occurs first.
Write Protect (WP). Write Protect is an input
that gives an additional hardware protection for
each block. When Write Protect is at VIL, the Lock-
Down is enabled and the protection status of the
Locked-Down blocks cannot be changed. When
Write Protect is at VIH, the Lock-Down is disabled
and the Locked-Down blocks can be locked or un-
locked. (refer to Table 16., Lock Status).
Reset (RP). The Reset input provides a hard-
ware reset of the memory. When Reset is at VIL,
the memory is in reset mode: the outputs are high
impedance and the current consumption is re-
duced to the Reset Supply Current IDD2. Refer to
value of IDD2. After Reset all blocks are in the
Locked state and the Configuration Register is re-
set. When Reset is at VIH, the device is in normal
operation. Exiting reset mode the device enters
asynchronous read mode, but a negative transi-
tion of Chip Enable or Latch Enable is required to
ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to VRPH
Latch Enable (L). Latch Enable latches the ad-
dress bits on its rising edge. The address
latch is transparent when Latch Enable is at
VIL and it is inhibited when Latch Enable is at
VIH. Latch Enable can be kept Low (also at
board level) when the Latch Enable function
is not required or supported.
Clock (K). The clock input synchronizes the
memory to the microcontroller during synchronous
read operations; the address is latched on a Clock
edge (rising or falling, according to the configura-
tion settings) when Latch Enable is at VIL. Clock is
ignored during asynchronous read and in write op-
erations.
Wait (WAIT). Wait is an output signal used during
synchronous read to indicate whether the data on
the output bus are valid. This output is high imped-
ance when Chip Enable is at VIH, Output Enable is
at VIH, or Reset is at VIL. It can be configured to be
active during the wait cycle or one data cycle in ad-
vance.
VDD Supply Voltage . VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
VDDQ Supply Voltage. VDDQ provides the power
supply to the I/O pins and enables all Outputs to
be powered independently of VDD. VDDQ can be
tied to VDD or can use a separate supply.
VPP Program Supply Voltage. VPP is both a
control input and a power supply pin. The two
functions are selected by the voltage range ap-
plied to the pin.
If VPP is kept in a low voltage range (0V to VDDQ)
VPP is seen as a control input. In this case a volt-
age lower than VPPLK gives an absolute protection
against program or erase, while if VPP is within the
VPP1 range these functions are enabled (see Ta-
values). VPP is only sampled at the beginning of a
program or erase; a change in its value after the
operation has started does not have any effect and
program or erase operations continue.
If VPP is in the range of VPPH it acts as a power
supply pin. In this condition VPP must be stable un-
til the Program/Erase algorithm is completed.
相關PDF資料 |
PDF描述 |
|---|---|
| M30L0T8000B0ZAQE | 16M X 16 FLASH 1.8V PROM, 85 ns, PBGA88 |
| M31002AMLJ1000.000000MHZ | VCXO, CLOCK, 1000 MHz, LVDS OUTPUT |
| M31016AUMJ1000.000000MHZ | VCXO, CLOCK, 1000 MHz, CMOS OUTPUT |
| M31002AGMJ1000.000000MHZ | VCXO, CLOCK, 1000 MHz, CMOS OUTPUT |
| M31002BMMJ1000.000000MHZ | VCXO, CLOCK, 1000 MHz, CMOS OUTPUT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M30L0R8000B0ZAQF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000B0ZAQT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
| M30L0R8000T0ZAQE | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Mbit (16Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復。