參數(shù)資料
型號: LXP730LE
元件分類: 通信及網(wǎng)絡
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 60/70頁
文件大?。?/td> 1007K
代理商: LXP730LE
LXP730
Multi-Rate DSL Framer
60
Datasheet
5.12
Codec Configuration Register
Address: 22
Abbreviation: COD_CFG
Read/Write
5.13
Overhead Registers (25 bytes)
5.13.1
Miscellaneous Control
Address: 23
Abbreviation: MISC_CTL
Read/Write
Table 56. PCM 2 Configuration Bits
Bit
Name
Default
Description
7
T1E1/PCM
0
T1E1 - PCM selection, 0 = PCM mode, 1 = T1E1 mode.
6
T1E1
1
T1/E1 selection, 0 = T1 frame mode, 1 = E1 frame mode.
<5:0>
MAXPCHN
1Fh
Max Number of PCM Channels, values 0 - 63, MAXPCHN + 1 = n
PCM channels between PCM sync pulses.
Table 57. Codec Configuration
Bit
Name
Default
Description
<7:6>
CCLKMUX
10b
Codec Clock Mux
00 External Pin, PCLK pin-14
01 Internal ADPLL
10 MCLK divided by PROG_DIV register
11 ADPLL output divided by PROG_DIV register
<0:5>
MAXCCHN
1Fh
Max Number of codec channels, values 0 - 31, MAXCCHN + 1 = n
codec channels between codec sync pulses.
Table 58. Miscellaneous Control
Bit
Name
Default
Description
<7:6>
LOS_SEL
00b
LOS Select, for outgoing MX direction
00 set LOS based on PCLK
01 set LOS based on codec clock
10 disable LOS; set
1
to LOSD on TX DSL frame
11 enable LOS, for testing; set
0
to LOSD on TX DSL frame
5
CCLKMODE
0
Set to
0
for 1x clock, set to
1
for 2x clock.
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